SMPS Input Filter Designer: Middlebrook Stability and Damping
Check whether an LC input filter threatens converter stability. Compare RC and RL damping, two-stage filters, ripple attenuation, losses and small-signal transients.
An input LC filter can reduce switching ripple while making a regulated converter harder to stabilize. As input voltage falls, a converter that maintains output power draws more current. This negative incremental input resistance can feed energy into the filter resonance. The SMPS input filter designer helps engineers and students explore that interaction before choosing components.
Start with the DC voltage at the converter terminals, output power, and efficiency. Enter effective capacitance after voltage-bias derating, winding resistance, capacitor ESR, and source or cable resistance. Set the upper frequency over which constant-power behavior is a reasonable approximation, usually within the regulation bandwidth. Include the converter’s local input capacitance in the final filter capacitor.
The Middlebrook criterion calculator compares filter output impedance with the magnitude of −V²/P. It reports the worst separation from DC through the model band and refines resonant peaks between samples. Positive separation means the magnitude ratio stays below unity in that band; the default design goal adds 6 dB of clearance. Failure of this sufficient screen calls for further analysis, rather than establishing oscillation. The input-impedance envelope ends at the declared model frequency on the Bode plots.
Compare no added damping, a parallel RC leg across each capacitor, or a series RL leg across each inductor. Automatic sizing minimizes the ideal isolated stage’s output-impedance peak for the chosen storage ratio. Enter manual values to evaluate available parts. Actual responses include the entered parasitics and coupled stage loading. Two-stage mode solves both LC sections together.
For a buck converter input filter, specify an independently injected sinusoidal current harmonic and its RMS amplitude. Within the constant-power band, the predicted source current, terminal ripple, and resistor heating include converter loading. Above that band, they assume negligible incremental converter loading. The chart distinguishes passive insertion from the CPL-loaded harmonic response. These are model estimates, especially near component self-resonance.
Specify allowed source ripple, or reduction from a measured conducted-emission baseline with consistent detector, bandwidth, LISN, and setup. Emission-baseline verdicts are withheld inside the converter model band because that reduction needs loaded measurements. CISPR is relevant to measurement planning; this tool contains no standard limit tables or compliance decision. If the predicted harmonic voltage peak, √2 times RMS, exceeds 5% of DC input voltage, both stability and target verdicts are withheld. Reduce the injected current or revise the filter.
The LC filter damping calculator also shows a source-step transient and moving cursor around an already powered operating point. A balanced matrix pole calculation checks numerical conditioning. Growing responses stop only at a verified 5% boundary crossing. A computation limit is identified separately. Pole and transient models extend ideal constant-power behavior to every frequency, so verify modes outside the declared band using measured impedance.
An RC blocking capacitor removes steady damper DC loss. A real RL bypass can carry some DC because the main winding has resistance. Reported resistor heating includes DC and one harmonic, using the actual branch voltage difference. Add other harmonics and check ratings separately. Startup, hot plugging, saturation, ESL, common-mode noise, and detailed converter control require other models or measurements.
How it is calculated
Converter and impedance screen
Use and , with voltage measured at the converter terminals. MIT 6.622 Lecture 29, pp. 5–6, explains the constant-power approximation and impedance separation; Middlebrook’s extra element theorem supplies the interaction framework.
With the source voltage set to zero, solve the passive ladder for . A main capacitor contributes . An RC damper adds in shunt. An RL damper places in parallel with the main winding impedance. Source resistance precedes the first section. Cascaded stages are coupled exactly by series/parallel impedance reduction.
Report from DC to the declared constant-power frequency. A logarithmic search locates candidate resonances, then bounded optimization refines each sampled peak. The desired separation is a user-selected engineering allowance, not a standard requirement.
Damping selection
For an ideal isolated RC-damped stage, let and :
This minimizes output-impedance peaking (MIT Lecture 29, p. 4; Erickson 1999). Subtract damping-capacitor ESR to suggest a discrete resistor. A 1 mΩ lower bound is flagged when ESR exhausts the resistance budget.
For the dual RL topology with , equal-fixed-point analysis gives
These are starting values for each isolated stage. They do not globally optimize a cascaded filter or account for parasitics in the optimum itself; the subsequent response does include the entered parasitics.
Attenuation, loss and transient
The unloaded passive voltage transfer also equals the reverse source-current / injected-converter-current transfer by reciprocity. For an independently injected current harmonic within the declared constant-power band:
Above that band the incremental converter loading is omitted, so and . Current-harmonic attenuation is . The passive insertion and in-band CPL-loaded curves are identified separately.
Use to test the 5% operating-point boundary. No passing stability or target verdict is issued outside that boundary. Emission-baseline verdicts are also withheld inside the regulation band; they need loaded measurements rather than an assumed unchanged emission source.
Resistor ripple loss is using RMS phasors and the same loading factor. For the first RL leg, recover the source-side node after source resistance, , then use . This retains the voltage across the inductor instead of grounding its upstream node. DC sharing includes winding resistance in the RL bypass.
The transient solves KCL and KVL with load conductance . A normalized state matrix and matrix exponential give the sampled source-step response, equivalent to . Stable cases propagate through the entire requested window. If a sample brackets a 5% crossing, bisection with matrix-exponential propagation locates the crossing and sets an explicit event flag. A separate flag reports a computation limit; elapsed duration alone never implies a crossing. Peak perturbation is a sampled value. Animation only interpolates the precomputed trace.
Poles come directly from a diagonally balanced real Schur decomposition, extracting its 1×1 and 2×2 blocks. The calculation checks the reconstruction residual, orthogonality, neglected lower-block entries and balancing spread. Shifted inverse iteration estimates left/right eigenvalue condition numbers and residuals; a conservative numerical allowance must leave the pole sign resolved. Failed checks or marginal signs produce an unresolved verdict.
Assumptions
- The converter alone is stable and operates around a fixed DC point with constant efficiency.
- Constant-power impedance is applicable only over the declared band for the magnitude screen. The transient and pole calculation extend that approximation to all frequencies.
- Components are linear and lumped. Main capacitor ESR and inductor DC resistance are constant with frequency. The damping inductor is ideal; damping-capacitor ESR is entered separately.
- Both stages use the same damping topology and storage ratio. Local converter capacitance belongs in the final shunt capacitor.
- Source impedance is a real resistance; no upstream control dynamics or cable inductance beyond the entered filter inductors is modeled.
- The harmonic input is an independent sinusoidal current source excluding incremental converter response. Converter loading is within the declared band and neglected above it. The 5% limit applies to peak terminal voltage, not RMS.
Where it applies
Use this as a small-signal design screen, then verify the converter’s measured input impedance and the assembled filter. Meeting a magnitude criterion within a limited band is not a proof of complete system stability. A failed screen is inconclusive by itself; an unstable ideal-CPL pole is a prediction of that stated model.
Enter a source step no larger than 1% of DC terminal voltage. Traces stop at an explicitly located 5% crossing, where linear predictions should no longer be extrapolated. A computation limit has its own status and never claims a boundary crossing. This is not a startup, hot-plug, inrush or protection simulation. Review damping-resistor pulse energy separately for those events.
ESL, inductor self-resonance, saturation, core loss, temperature dependence, common-mode paths, layout coupling, switching dynamics and detailed control impedance are excluded. High-frequency attenuation is therefore an estimate below component self-resonance. DC losses include source and winding resistance; the damping-resistor result excludes capacitor ESR and magnetic losses.
Harmonic voltage is checked using peak = √2 × RMS, with converter loading included inside the model band. Outside the 5% boundary, numerical loss and ripple values are linear extrapolations and the passing stability/target verdicts are withheld. Unresolved numerical pole signs likewise withhold target acceptance.
For conducted emissions, enter the applicable target and use the prescribed measurement setup. Baseline-reduction verdicts inside the converter model band are withheld pending loaded measurements. No CISPR limits or detector models are implemented. Check against the standard in force; a calculated attenuation does not certify compliance.
References
- MIT OpenCourseWare, D. Perreault, 6.622 Power Electronics, Spring 2023, Lecture 29, EMI Filtering 2, pp. 3–6. https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf
- M. Sclocchi, Input Filter Design for Switching Power Supplies, TI SNVA538 (2010), PDF pp. 14–17 worked example. https://www.ti.com/lit/an/snva538/snva538.pdf
- R. W. Erickson, Optimal Single-Resistor Damping of Input Filters, APEC 1999, pp. 1073–1079. DOI: 10.1109/APEC.1999.750502
- R. D. Middlebrook, Input Filter Considerations in Design and Application of Switching Regulators, IEEE IAS Annual Meeting (1976), pp. 366–382; foundational magnitude-separation method. For the extra element theorem: Null Double Injection and the Extra Element Theorem (1989), DOI: 10.1109/13.34149, open repository https://authors.library.caltech.edu/records/2kkth-50y81
- F. C. Lee and S. S. Kelkar, Input Filter Compensation for Switching Regulators, NASA-CR-169005 (1982); context on filter/control interaction and active compensation, not the passive sizing equations used here. https://ntrs.nasa.gov/citations/19820017566
- math.js real Schur matrix decomposition and eigenvalue accuracy/conditioning guidance: https://mathjs.org/docs/reference/functions/schur.html and https://mathjs.org/docs/reference/functions/eigs.html . The calculator checks decomposition residuals and eigenvalue sensitivity rather than relying on polynomial roots.
Inputs
| Input | Symbol | Unit | Default |
|---|---|---|---|
| Filter stages | stages | One LC stage | |
| Damping topology Parallel RC places a resistor and blocking capacitor in series across each main capacitor. Series RL places a resistor and damping inductor in series across each main inductor. | damping | Parallel RC damping | |
| Damping resistor selection Automatic sizing minimizes the ideal isolated stage's output-impedance peak. The computed response includes parasitics, source resistance and stage loading. | sizing | Ideal-stage impedance optimum | |
| DC voltage at converter terminals | V_in | V | 24 |
| Converter output power | P_out | W | 120 |
| Converter efficiency Enter a fraction, e.g. 0.90. Input power is output power divided by efficiency. | efficiency | 0.9 | |
| Constant-power model upper frequency Usually no higher than the converter regulation bandwidth. Verify measured input impedance above this band. | f_band | kHz | 30 |
| Source and cable resistance | R_source | ohm | 0.05 |
| Stage 1 inductance | L_1 | uH | 10 |
| Stage 1 effective capacitance Use capacitance after DC-bias and temperature derating; include local converter input capacitance here in one-stage mode. | C_1 | uF | 47 |
| Stage 1 inductor DC resistance | r_1 | ohm | 0.03 |
| Stage 1 capacitor ESR | es_1 | ohm | 0.03 |
| Stage 2 inductance | L_2 | uH | 22 |
| Stage 2 effective capacitance | C_2 | uF | 47 |
| Stage 2 inductor DC resistance | r_2 | ohm | 0.04 |
| Stage 2 capacitor ESR | es_2 | ohm | 0.03 |
| Damping capacitance / main capacitance Applied to both stages. MIT gives 2–10 as a typical range. | n_C | 4 | |
| Damping inductance / main inductance Applied to both stages. A smaller damping inductor reduces impedance but weakens high-frequency attenuation. | n_L | 0.13333333333333333 | |
| RC damping capacitor ESR, each stage The suggested discrete resistor subtracts this ESR from the ideal total branch resistance. | es_d | ohm | 0.04 |
| Stage 1 discrete damping resistor | R_manual1 | ohm | 0.47 |
| Stage 2 discrete damping resistor | R_manual2 | ohm | 0.68 |
| Desired impedance separation In dB: 6 dB means |Zo| must remain below half of |Zin| within the modeled band. | margin_goal | 6 | |
| Ripple / emission target frequency Usually the switching frequency or a troublesome harmonic. Current estimates include CPL loading within the declared model band and neglect incremental converter loading above it. | f_noise | kHz | 200 |
| Independent injected harmonic current (RMS) An independent sinusoidal current source at the converter node, excluding incremental converter current. CPL loading is included within the declared band; the peak terminal voltage must remain below 5% of DC. | I_noise | A | 0.5 |
| Attenuation requirement | target_mode | Allowed source ripple current | |
| Allowed source ripple current (RMS) | I_allow | A | 0.005 |
| Measured baseline emission (dBµV) Baseline without this filter, at the target frequency, with the same detector, bandwidth, LISN and setup as the target. | level_before | 80 | |
| Engineering emission target (dBµV) Enter your applicable target; no CISPR limit table or compliance verdict is built in. | level_limit | 46 | |
| Extra attenuation allowance (dB) | atten_margin | 6 | |
| Small source-voltage step Perturbation about the powered operating point, with constant output power. This is not a startup or hot-plug simulation. | V_step | V | 0.1 |
| Transient window (slow LC periods) | cycles | 6 | |
| ▶ Transient cursor Play moves the voltage marker along the precomputed response. The trace stops at a 5% voltage perturbation. | t_play | ms | 0.06 |
Results
With the default inputs above, the calc gives:
| Result | Value |
|---|---|
| Middlebrook screen | Meets the requested separation in the modeled band |
| Impedance separation (dB) | 23.4148 |
| Damping components | Stage 1: R = 0.242 Ω, C = 188 µF |
| Attenuation target | Meets the entered attenuation target under the stated model |
| Attenuation headroom (dB) | 6.1273 |
| Current-harmonic attenuation at target (dB) | 52.1273 |
| Peak |Zo| in modeled band | 0.2916 Ω |
| Negative incremental Zin | -4.32 Ω |
| Worst impedance frequency | 4,875.4671 Hz |
| Source and filter DC loss | 2.4691 W |
| Damping resistor loss: DC + one harmonic | 0.0007 W |
| Source harmonic current (RMS) | 0.0012 A |
| Ideal constant-power dynamics | Decaying modes in the ideal constant-power model |
| Transient validity | Requested window completed within the 5% boundary |
| Converter-terminal harmonic voltage (peak) | 0.022 V |
Checked against sources
Each case below was calculated by this calc and agrees with the value from its source (within the tolerance where one is shown).
TI SNVA538: 33 µH / 47 µF LC worked example
Source: TI SNVA538, PDF pp. 14 and 16 (counting cover as p. 1): Lf = 33 µH, Cf = 47 µF, fcfilter1 = 4.041 kHz; sqrt(Lf/Cf) = 0.838 Ω. The note's positive Rin load is not used as a regulated converter impedance here.
Inputs: Damping topology = No added damping; Stage 1 inductance = 33 uH; Stage 1 capacitor ESR = 0.15 Ω; Source and cable resistance = 0 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Stage 1 undamped LC frequency | 4,041 Hz | 4,041 Hz |
| Stage 1 characteristic impedance | 0.838 Ω | 0.8379 Ω |
TI SNVA538: RC damping capacitor worked example
Source: TI SNVA538, PDF p. 16: Rd = sqrt(Lf/Cf) = 0.838 Ω; Cd = 4 Cf = 188 µF, ESRcd = 0.200 Ω. This published Rd rule differs from the minimum-output-impedance optimum implemented in automatic mode; manual mode reproduces the stated circuit.
Inputs: Damping resistor selection = Enter resistor values; Stage 1 inductance = 33 uH; Stage 1 capacitor ESR = 0.15 Ω; Source and cable resistance = 0 Ω; Stage 1 discrete damping resistor = 0.838 Ω; RC damping capacitor ESR, each stage = 0.2 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Stage 1 RC capacitance for reporting | 188 uF | 188 uF |
| Stage 1 characteristic impedance | 0.838 Ω | 0.8379 Ω |
TI SNVA538: RL damping inductor worked example
Source: TI SNVA538, PDF p. 17: n3 = 2/15, Ld = Lf n3 = 4.4 µH, Rds = sqrt(Lf/Cf) = 0.838 Ω. The manual circuit follows the published component choice; optimum output-impedance damping is a different objective.
Inputs: Damping topology = Series RL damping; Damping resistor selection = Enter resistor values; Stage 1 inductance = 33 uH; Stage 1 capacitor ESR = 0.15 Ω; Source and cable resistance = 0 Ω; Stage 1 discrete damping resistor = 0.838 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Stage 1 RL inductance for reporting | 4.4 uH | 4.4 uH |
| Stage 1 characteristic impedance | 0.838 Ω | 0.8379 Ω |
MIT ideal RC optimum: n = 4 normalized benchmark
Source: MIT 6.622 Lecture 29, PDF p. 4, published ideal-stage minimax equations evaluated at n = 4 and Zc = 1 Ω: Rd/Zc = sqrt(3/8), max|Zo|/Zc = sqrt(12)/4. A 10 nΩ winding resistance makes the undamped comparison finite without changing these benchmark results to the stated tolerance.
Inputs: Stage 1 inductance = 100 uH; Stage 1 effective capacitance = 100 uF; Source and cable resistance = 0 Ω; Stage 1 inductor DC resistance = 1 × 10⁻⁸ Ω; Stage 1 capacitor ESR = 0 Ω; RC damping capacitor ESR, each stage = 0 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Ideal stage 1 optimum total damping resistance | 0.6124 Ω | 0.6124 Ω |
| Peak |Zo| in modeled band | 0.866 Ω | 0.866 Ω |
Stiff two-stage RL: 100 Ω, Ld/L = 0.01
Source: Independent SI modified-nodal state model in review_crosscheck.py, evaluated with SciPy 1.15.3 LAPACK eigenanalysis and scipy.linalg.expm (no catalog-file reads). KCL/KVL and negative-resistance method: MIT 6.622 Lecture 29, pp. 5–6, https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf . Regression from review #972; values do not come from a characteristic polynomial.
Inputs: Filter stages = Two LC stages; Damping topology = Series RL damping; Damping resistor selection = Enter resistor values; Damping inductance / main inductance = 0.01; Stage 1 discrete damping resistor = 100 Ω; Stage 2 discrete damping resistor = 100 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Largest computed pole real part; use the numerical status | -668.2 1/s | -668.2 1/s |
| Largest absolute converter voltage perturbation | 0.2222 V | 0.2222 V |
| End of the valid computed transient | 0.001212 s | 0.001212 s |
| Transient event: 0 complete, 1 crossing, 2 limit, 3 invalid | 0 | 0 |
| Pole classification: −1 decaying, +1 growing, 0 unresolved | -1 | -1 |
Stiff two-stage RL: 1000 Ω, Ld/L = 0.01
Source: Independent SI modified-nodal state model in review_crosscheck.py, evaluated with SciPy 1.15.3 LAPACK eigenanalysis and scipy.linalg.expm (no catalog-file reads). KCL/KVL and negative-resistance method: MIT 6.622 Lecture 29, pp. 5–6, https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf . Regression from review #972; values do not come from a characteristic polynomial.
Inputs: Filter stages = Two LC stages; Damping topology = Series RL damping; Damping resistor selection = Enter resistor values; Damping inductance / main inductance = 0.01; Stage 1 discrete damping resistor = 1,000 Ω; Stage 2 discrete damping resistor = 1,000 Ω; the others as above.
| Result | Source | This calc |
|---|---|---|
| Largest computed pole real part; use the numerical status | -624.3 1/s | -624.3 1/s |
| Largest absolute converter voltage perturbation | 0.2231 V | 0.2231 V |
| End of the valid computed transient | 0.001212 s | 0.001212 s |
| Transient event: 0 complete, 1 crossing, 2 limit, 3 invalid | 0 | 0 |
| Pole classification: −1 decaying, +1 growing, 0 unresolved | -1 | -1 |
RL damper uses the node after the nonzero source resistance
Source: Independent SI modified-nodal phasor model in review_crosscheck.py, solved using NumPy 2.0.2; the source-side node, winding and damping branches are separate nodes and admittances. CPL conductance is -P/V² when loaded. No catalog-file reads. Method: MIT 6.622 Lecture 29 pp. 5–6, https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf . R_source = 0.05 Ω, f = 100 Hz, I_h = 0.5 A RMS. The passive result isolates the source-node correction; the loaded result also includes the converter.
Inputs: Damping topology = Series RL damping; Ripple / emission target frequency = 0.1 kHz; the others as above.
| Result | Source | This calc |
|---|---|---|
| Passive discrete-damper harmonic loss for comparison | 8.761 × 10⁻⁴ W | 8.761 × 10⁻⁴ W |
| Discrete-damper harmonic loss, loaded within model band | 9.079 × 10⁻⁴ W | 9.079 × 10⁻⁴ W |
| Source harmonic current (RMS) | 0.5091 A | 0.5091 A |
In-band CPL loading changes a passing passive target to a failing target
Source: Independent SI modified-nodal phasor model in review_crosscheck.py, solved using NumPy 2.0.2; the source-side node, winding and damping branches are separate nodes and admittances. CPL conductance is -P/V² when loaded. No catalog-file reads. Method: MIT 6.622 Lecture 29 pp. 5–6, https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf . At 6 kHz the current source is independent of terminal voltage, while the converter contributes negative incremental admittance. Source resistance is zero, enforced as an ideal voltage-source constraint.
Inputs: Converter output power = 1,000 W; Source and cable resistance = 0 Ω; Ripple / emission target frequency = 6 kHz; Independent injected harmonic current (RMS) = 0.01 A; Allowed source ripple current (RMS) = 0.01 A; Desired impedance separation = 0; Extra attenuation allowance (dB) = 0; the others as above.
| Result | Source | This calc |
|---|---|---|
| Source harmonic current with converter loading omitted | 0.008304 A | 0.008304 A |
| Source harmonic current (RMS) | 0.01995 A | 0.01995 A |
| Discrete-damper harmonic loss, loaded within model band | 1.384 × 10⁻⁴ W | 1.384 × 10⁻⁴ W |
1000 A harmonic cannot receive a passing small-signal target verdict
Source: Independent SI modified-nodal phasor model in review_crosscheck.py, solved using NumPy 2.0.2; the source-side node, winding and damping branches are separate nodes and admittances. CPL conductance is -P/V² when loaded. No catalog-file reads. Method: MIT 6.622 Lecture 29 pp. 5–6, https://ocw.mit.edu/courses/6-622-power-electronics-spring-2023/mit6_622_s23_lec292.pdf . The deliberately excessive current is outside the model domain: its linear extrapolation checks the √2 RMS-to-peak guard and withheld verdict, not a realizable operating-point prediction.
Inputs: Independent injected harmonic current (RMS) = 1,000 A; Allowed source ripple current (RMS) = 5 A; the others as above.
| Result | Source | This calc |
|---|---|---|
| Converter-terminal harmonic voltage (RMS) | 31.107 V | 31.107 V |
| Converter-terminal harmonic voltage (peak) | 43.992 V | 43.992 V |
| Harmonic inside the small-signal range (1 yes, 0 no) | 0 | 0 |
| Predictive target verdict enabled (1 yes, 0 no) | 0 | 0 |
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