SMPS Input Filter Designer: Middlebrook Stability and Damping

Converter and impedance screen

Use $P_{in}=P_{out}/\eta$ and $Z_{in}=-V_{in}^{2}/P_{in}$, with voltage measured at the converter terminals. MIT 6.622 Lecture 29, pp. 5–6, explains the constant-power approximation and impedance separation; Middlebrook’s extra element theorem supplies the interaction framework.

This does not model the converter-specific $Z_N(s)$ and $Z_D(s)$ in Erickson and Maksimović, Fundamentals of Power Electronics, 2nd ed. (2001), Eq. (10.13). $Z_N$ is the converter input impedance with output-voltage perturbation nulled by ideal regulation; $Z_D$ is its input impedance with duty perturbation held at zero. Only the low-frequency constant-power approximation is used here. The full pair of inequalities needed to preserve the converter transfer function is not evaluated.

With the source voltage set to zero, solve the passive ladder for $Z_o$. A main capacitor contributes $Y_C=sC/(1+sC\,ESR)$. An RC damper adds $sC_d/[1+sC_d(R_d+ESR_d)]$ in shunt. The parallel R–L damper places $R_d+sL_d$ in parallel with the main winding impedance: its resistor and auxiliary inductor form a series branch across $L_f$ (Erickson Fig. 10.20b). The separate series-damping circuit of Fig. 10.20c and Eqs. (10.39)–(10.41) is not implemented. Source resistance precedes the first section. Cascaded stages are coupled exactly by series/parallel impedance reduction. For this connected LC ladder, a positive source resistance, winding resistance or capacitor ESR anywhere damps the passive undamped-comparison network; each section need not have its own loss. A completely lossless comparison is excluded.

Report $M=20\log_{10}(|Z_{in}|/\max|Z_o|)$ from DC to the declared constant-power frequency. A logarithmic search locates candidate resonances, then bounded optimization refines each sampled peak. The desired separation is a user-selected engineering allowance, not a standard requirement.

Damping selection

For an ideal isolated RC-damped stage, let $Z_c=\sqrt{L/C}$ and $n=C_d/C$:

This minimizes output-impedance peaking (MIT Lecture 29, p. 4; Erickson and Maksimović, 2nd ed., Chapter 10, Eqs. (10.28)–(10.31), especially Eq. (10.31); Erickson 1999). Subtract damping-capacitor ESR to suggest a discrete resistor. A 1 mΩ lower bound is flagged when ESR exhausts the resistance budget.

For the parallel R–L topology of Fig. 10.20b, with $n=L_d/L=L_b/L_f$, Eq. (10.34) gives

The parallel R–L design and peak relations are covered by Eqs. (10.34)–(10.37). At high frequency, $L_{eq}=L_f L_b/(L_f+L_b)$, so Eq. (10.38) raises the ideal single-section gain asymptote by $1+1/n$ relative to the undamped filter. This reduces attenuation by $20\log_{10}(1+1/n)$ dB per ideal section; the default $n=2/15$ costs approximately 18.6 dB. The ideal two-pole slope remains −40 dB/decade. The plotted circuit response already includes this trade-off; do not subtract the penalty again.

These are starting values for each isolated stage. They do not globally optimize a cascaded filter or account for parasitics in the optimum itself; the subsequent response does include the entered parasitics.

Attenuation, loss and transient

The unloaded passive voltage transfer $H$ also equals the reverse source-current / injected-converter-current transfer by reciprocity. For an independently injected current harmonic within the declared constant-power band:

Above that band the incremental converter loading is omitted, so $G_I=H$ and $V_{rms}=|I_hZ_o|$. Current-harmonic attenuation is $-20\log_{10}|G_I|$. The passive insertion and in-band CPL-loaded curves are identified separately.

The required reduction retains its sign: $A_{req}=20\log_{10}(I_h/I_{allow})+M_A$ for ripple current, or $A_{req}=L_{before}-L_{target}+M_A$ for emission levels. A negative requirement preserves headroom already present. Compare the predicted attenuation against this signed value; equivalently, compare source current against $I_{allow}/10^{M_A/20}$. No reduction is clamped to zero.

Use $V_{pk}=\sqrt{2}V_{rms}$ to test the 5% operating-point boundary. No passing stability or target verdict is issued outside that boundary. Emission-baseline verdicts are also withheld inside the regulation band; they need loaded measurements rather than an assumed unchanged emission source.

Resistor ripple loss is $|I_d|^2R_d$ using RMS phasors and the same loading factor. For the first RL leg, recover the source-side node after source resistance, $v_u=v_1R_s/(R_s+Z_{L1})$, then use $(v_u-v_1)/(R_d+sL_d)$. This retains the voltage across the inductor instead of grounding its upstream node. DC sharing includes winding resistance in the RL bypass.

The transient solves KCL and KVL with load conductance $-1/|Z_{in}|$. A normalized state matrix and matrix exponential give the sampled source-step response, equivalent to $H/(1-Z_o/|Z_{in}|)$. Propagation intervals limit the fastest oscillatory pole’s phase advance to π/16 rad (32 intervals per period), and initial steps resolve the fastest real decay. Sign changes of the exact output derivative bracket extrema; 32 matrix-exponential bisections refine each extremum and add it to the trace. Each extremum is checked before the interval endpoint, so a narrow excursion above 5% is detected even if both sampled endpoints lie below it. Bisection then locates the first crossing on the preceding segment and sets an explicit event flag. Peak perturbation includes the refined extrema. Stable cases propagate through the requested window unless a crossing or computation limit intervenes. A separate flag reports a computation limit; elapsed duration alone never implies a crossing. Animation only interpolates the precomputed trace.

Poles come directly from a diagonally balanced real Schur decomposition, extracting its 1×1 and 2×2 blocks. The calculation checks the reconstruction residual, orthogonality, neglected lower-block entries and balancing spread. Shifted inverse iteration estimates left/right eigenvalue condition numbers and residuals; a conservative numerical allowance must leave the pole sign resolved. Failed checks or marginal signs produce an unresolved verdict.

• The converter alone is stable and operates around a fixed DC point with constant efficiency.
• The converter-specific $Z_N(s)$ and $Z_D(s)$ of Chapter 10, Eq. (10.13), and their control dynamics are not modeled.
• Constant-power impedance is applicable only over the declared band for the magnitude screen. The transient and pole calculation extend that approximation to all frequencies.
• Components are linear and lumped. Main capacitor ESR and inductor DC resistance are constant with frequency. The damping inductor is ideal; damping-capacitor ESR is entered separately.
• Both stages use the same damping topology and storage ratio. Local converter capacitance belongs in the final shunt capacitor.
• Source impedance is a real resistance; no upstream control dynamics or cable inductance beyond the entered filter inductors is modeled.
• The harmonic input is an independent sinusoidal current source excluding incremental converter response. Converter loading is $-1/|Z_{in}|$ within the declared band and neglected above it. The 5% limit applies to peak terminal voltage, not RMS.

Use this as a small-signal design screen, then verify the converter’s measured input impedance and the assembled filter. Meeting a magnitude criterion within a limited band is not a proof of complete system stability or a check of both converter-specific impedance inequalities in Erickson’s Eq. (10.13). Verify those impedances and loop gain for the actual converter. A failed screen is inconclusive by itself; an unstable ideal-CPL pole is a prediction of that stated model.

Enter a source step no larger than 1% of DC terminal voltage. Traces stop at an explicitly located 5% crossing, where linear predictions should no longer be extrapolated. A computation limit has its own status and never claims a boundary crossing. This is not a startup, hot-plug, inrush or protection simulation. Review damping-resistor pulse energy separately for those events.

ESL, inductor self-resonance, saturation, core loss, temperature dependence, common-mode paths, layout coupling, switching dynamics and detailed control impedance are excluded. High-frequency attenuation is therefore an estimate below component self-resonance. DC losses include source and winding resistance; the damping-resistor result excludes capacitor ESR and magnetic losses.

Harmonic voltage is checked using peak = √2 × RMS, with converter loading included inside the model band. Outside the 5% boundary, numerical loss and ripple values are linear extrapolations and the passing stability/target verdicts are withheld. Unresolved numerical pole signs likewise withhold target acceptance.

For conducted emissions, enter the applicable target and use the prescribed measurement setup. Baseline-reduction verdicts inside the converter model band are withheld pending loaded measurements. No CISPR limits or detector models are implemented. Check against the standard in force; a calculated attenuation does not certify compliance.