ESC Capacitor Sizing: Lead Inductance, Spikes and Ripple

The circuit follows Kirchhoff's voltage and current laws. The battery is an ideal open-circuit voltage behind an ohmic resistance and one polarization R–C element. Copper resistance uses both conductors and its temperature coefficient. For parallel round conductors the external loop inductance is $L'=\mu_0\operatorname{acosh}(s/d)/\pi$; total battery loop inductance adds the entered fixed parasitics.

Each capacitor branch contains its own series ESR, ESL and ideal capacitance. Identical electrolytics share current equally; their C adds, ESR and intrinsic ESL divide by count, and shared mounting inductance remains. With $i_c=i_b-i_e-i_{load}$, the five states are battery current, electrolytic current, both ideal capacitor voltages and battery polarization voltage. Eliminating the common bus voltage gives the linear state equations implemented in bus_rhs. Positive capacitor current charges a capacitor.

The inverter draws a trapezoidal pulse with linear rise and fall of duration $t_e$, pulse height $I_{phase}$, average $DI_{phase}$ and period $1/f_{PWM}$. Matrix exponentials integrate each edge and plateau exactly. A linear periodic boundary solve finds the initial state without a guessed settling time. Both sides of edge events are sampled. The MOSFET estimate is $v_{FET}=v_{bus}-L_{switch}\,di_{load}/dt$; battery lead inductance is not added to this local spike again.

RMS currents and energy/charge balances use event-aligned time quadrature. ESR heating is $I_{rms}^2R$ and temperature rise is loss times entered thermal resistance. The corrected ripple rating is the data-sheet rating times the entered correction factor. Design scans solve the same circuit impedances for the finite-edge pulse harmonics; Parseval gives branch RMS, and an inverse FFT reconstructs bus voltage after removing and analytically restoring its algebraic ESL edge jump. Every scan point also solves the exact periodic state transitions at all four switching events and evaluates each endpoint with both one-sided current slew rates. The larger of these event peaks and the harmonic-grid peaks is used, so an edge cannot disappear between FFT samples. Scan voltage envelopes use peak bus voltage plus the positive local L·di/dt bound. Bank options test all entered limits.

TI SLTA055 pp. 2–4 supplies the ideal pulse-ripple comparison and independent published examples. TI SLVAFT0 pp. 3–6 motivates retaining lead inductance and real capacitor impedance. Infineon's BTN7030 guidance and Flycolor's manual p. 2 support placing the bulk capacitor close to the drive.

The electrical equations and exact state-transition algorithm are derived here. A fixed conducting phase-pair current represents six-step motoring over one PWM period; current ripple within the motor winding and changes across an electrical revolution are not generated by this model. Duty describes the bus-current pulse, not a commanded throttle percentage. The battery can source or absorb the small switching ripple about its average operating point.

Capacitance, ESR, ESL and battery parameters are linear and constant over each run. ESR and effective ceramic capacitance must represent operating temperature, bias and frequency. Parallel electrolytics are identical and equally connected. The thermal resistances are user estimates, and mutual heating between cans is not included.

Illustrative electrolytic defaults use the Panasonic EEUFR1V102 nominal 1000 µF, 35 V and 2.6 A at 100 kHz. The 18 mΩ default is an approximation based on its maximum impedance, not a separately specified broadband ESR. The entered 0.8 rating factor, ESL values, thermal resistances, battery parameters and ceramic bank are editable engineering assumptions. For minimum capacitance sizing, include the part's negative tolerance.

This is a linear periodic bus model, not a transient start-up, regenerative-braking, plug-in or fault model. It does not predict MOSFET avalanche, Coss/nonlinear switching, reverse recovery, snubbers, clamps, gate voltage or distributed transmission-line effects. The local L·di/dt voltage is an unclamped commutation estimate for the entered current edge; verify it at the device. No result establishes flight reliability.

The lead formula is the high-frequency external inductance of a long straight, close parallel pair in a nonmagnetic environment. Twisted, widely separated, branched or very short harnesses need measured inductance. Low-frequency internal conductor inductance, skin/proximity losses and frequency-dependent capacitor ESR are not fitted. The reported full-circuit ringing frequency and damping come from the oscillatory state-matrix pole; a zero frequency means that no oscillatory pole was found. The separate bulk LC reference is only a low-frequency approximation.

Default time-domain output uses 384 samples per plateau and 48 per edge, with exact propagation between samples. Peaks and RMS quadrature still require adequate sampling: double the time sampling input until changes are acceptable. Default design scans retain 255 harmonics and solve 41 lead lengths plus nine bank options. Adding exact one-sided switching-event solutions at every scan point took the previous resolution beyond about three seconds; the plateau sample count and lead grid are reduced to retain the full circuit physics within that budget. Switching-event peaks are evaluated exactly regardless of harmonic cutoff or FFT phase. Between events, harmonic reconstruction can still miss high-frequency content above its cutoff. The coarser lead grid can miss a narrow resonance between solved lengths; the lead charts use shape-preserving interpolation through 161 display points, and decisions use only solved lengths. Increase harmonic refinement and lead scan points, and narrow the scan range near a boundary. A resolved full-circuit resonance should lie well below the highest retained harmonic.

Lead reach is the last sampled length before the first sampled MOSFET voltage-envelope exceedance, or the chosen scan upper limit when none occurs. It checks voltage only; current, ripple and heating must also pass. The positive envelope deliberately combines bus and local maxima even when they occur at different times. It is conservative in that timing combination, not a guarantee against unresolved parasitics or unsampled resonances. The first tested passing bank may be zero when no listed option meets every limit.

Temperature is ambient plus I²ESR heating, without an ESR/temperature feedback or a lifetime model. Apply manufacturer frequency and temperature rating corrections and validate actual airflow. The selected voltage fraction is a user design margin, not a manufacturer-approved derating rule.