LLC Resonant Converter Designer: Gain, ZVS and Stress

The sizing flow follows the reflected-load and tank-impedance method in onsemi AN-4151, attached file pages 4–5 and 11. Define $n=N_p/N_s$ (one secondary half for center tap), $k=1/2$ for half bridge and $k=1$ for full bridge. The bridge AC square-wave amplitude is $A=kV_{in}$ and tank gain is $M=nV_o/A$. At rated load, $R_o=V_o^2/P_o$, $R_{ac}=8n^2R_o/\pi^2$, $Z_r=Q R_{ac}$, $L_r=Z_r/(2\pi f_r)$, $C_r=1/(2\pi f_r Z_r)$ and $L_m=L_nL_r$. At load fraction $d$, the fixed resistive load is $R_o/d$ and $Q_d=dQ$.

The FHA curve is

The FHA peak is numerically maximized over $0.2\le f_n\le1$. The inductive boundary separately solves $\operatorname{Im}(Z_{in}/Z_r)=f_n-1/f_n+f_nL_n/[1+(f_nL_nQ_d)^2]=0$. Neither the FHA peak nor the boundary is a hardware ZVS guarantee.

The time-domain equations are derived here from Kirchhoff's laws, not fitted to FHA or measured gain. Normalize $x=v_{Cr,ac}/A$, $j=i_rZ_r/A$, $h=i_mZ_r/A$, $m=nV_o/A$ and $\theta=2\pi f_r t$. Within a positive bridge half-cycle, an active rectifier polarity $s=\pm1$ gives $x'=j$, $j'=1-x-sm$, $h'=sm/L_n$. When rectifiers are off, $j=h$, $x'=j$ and $j'=(1-x)/(1+L_n)$. Each segment has an analytical sinusoidal solution.

PO uses a positive rectifier interval followed by an off interval. NP uses negative then positive rectification. A bracketed scalar root and linear system enforce half-cycle antisymmetry, transition $j=h$, and charge balance $\int |j-h|d\theta=(\pi/f_n)8Q_dm/\pi^2$. Diode-current signs and off-state voltage limits are checked at both endpoints and every analytical interior extremum. The near-resonance linear systems enforce charge balance together with magnetizing-current periodicity (PO) or current continuity (NP), avoiding singular gain-only equations. Sign-bracketed root refinement stops on the physical transition/periodicity residual; vanishing intervals are allowed. Unsupported sequences are rejected. Frequency regulation selects the highest-frequency supported crossing in $0.55\le f_n\le1.8$, then refines the gain residual to convergence. The displayed error is $100(M_{FHA}/M_{TD}-1)$ at equal frequency.

Stress metrics use 401 samples per period; plotted waveforms and Cr RMS voltage use 301 samples. Power conservation is checked using exact input work from the half-cycle capacitor-voltage change against independently sampled rectifier output power. Cr, Lr and the physical transformer-primary winding carry $i_r$, including magnetizing current (onsemi AN-4151, attached page 4). The ideal transformer's reflected load-current component is $i_r-i_m$; secondary current is $n|i_r-i_m|$. Each symmetrical rectifier and each primary switch has RMS current equal to the corresponding whole-cycle waveform RMS divided by $\sqrt2$. Cr includes its $V_{in}/2$ bias for half bridge and zero bias for full bridge. Ideal diode reverse voltage is $V_o$ for a bridge or $2V_o$ for center tap.

Following the charge-based reasoning in TI SLUA923, use $Q_{req}=(2C_{oss}+C_{node})V_{in}$ per midpoint and $Q_{avail}=I_{comm}t_d$, where $I_{comm}=-i_r(0)$ must be positive. The full bridge applies this test to each simultaneously moving midpoint; the required charge per midpoint is unchanged. The separate triangular estimate $nV_o/(4f_sL_m)$ is illustrative and is not substituted for solved commutation current.

• Ideal linear Lr, Cr, shunt Lm, transformer and rectifier; zero winding resistance, core loss and diode drop.
• Stiff DC input and output capacitor. The target voltage and power define a resistive load; manual frequency operation changes actual output power with voltage squared.
• Symmetrical 50% bridge switching. Dead time and primary output capacitance affect only the separate ZVS charge screen; their influence on tank gain and stress waveforms is omitted.
• Effective Coss is a time-related capacitance at the applicable bus voltage, preferably from Qoss/Vin. Additional capacitance is per bridge midpoint.
• Fractional calculated turns ratios are design targets. Use real winding counts and recheck the tank in component-value mode.
• The schematic and animated current plot are original drawings. The equations for the exact segment solver are derived here; the references establish conventional FHA design and operating-mode context.

Use $2\le L_m/L_r\le12$, rated-load $0.1\le Q\le1$ and $0.55\le f_s/f_r\le1.8$ for the displayed exact sweep. The solver is exact within the stated ideal PO and NP sequences, apart from numerical root tolerances and waveform sampling. It is not a universal solver for every LLC operating mode: low-load off intervals, PON and other sequences may be unsupported, and a gap is not a physical infeasibility conclusion.

An input-range result covers only minimum, nominal and maximum voltage at the currently selected load. It does not certify all intermediate voltages, all loads or component tolerances. Inspect other load fractions and recheck device capacitance versus bus voltage. Minimum gain at very light load may require burst control, which is omitted.

A positive charge margin is a screening result, not a ZVS guarantee. The current is held constant during the estimated transition; nonlinear capacitance, rectifier commutation, dead-time current reversal, driver delays and excessive dead time can invalidate it. Keep dead time small relative to the switching period and verify actual waveforms.

Component stresses are steady-state ideal values at the selected point or the three labelled line points, not voltage/current ratings. Add transient, overload, ringing, temperature and tolerance allowances. The tool does not calculate efficiency, thermal limits, core flux or isolation. FHA-versus-model error is not measurement accuracy, and no universal 10–15% correction is applied.