PWM Simulator: SPWM, SVPWM and Discontinuous PWM

The reference phase commands are $r_a=m_a\cos\theta$, $r_b=m_a\cos(\theta-120^\circ)$ and $r_c=m_a\cos(\theta+120^\circ)$, with $m_a=4M_i/\pi$ and carrier limits ±1. An identical zero sequence is added to all three phases, so it cancels from line-to-line voltage. Upper duty is $d_x=(1+r_x+z)/2$.

SPWM uses zero injection. SVPWM uses $z=-(\max r_x+\min r_x)/2$. THIPWM here means one-sixth injection, $z=-m_a\cos(3\theta)/6$. DPWM0, 1 and 2 select the largest absolute phase reference after rotating the selection signals by −30°, 0° and +30° respectively, then clamp the corresponding original phase to its rail. DPWM3 selects the intermediate absolute magnitude. See PESC author copy, pp. 3–4, magnitude rules, and APEC author copy, p. 3, equations (2)–(4).

The HDF polynomials are PESC p. 7, equations (26)–(35), evaluated first at the actual carrier frequency. $I_h=V_{dc}\sqrt{HDF}/(24 L_\sigma f_c)$ from equation (36) gives each phase’s RMS switching ripple. $THD_h=100 I_h/I_1$. Both are high-frequency inductive estimates.

For a DPWM method, equal average switching frequency means $f_c=1.5f_b$. The plotted base-frequency HDF is $HDF_b=HDF/(f_c/f_b)^2$, so $I_h=V_{dc}\sqrt{HDF_b}/(24L_\sigma f_b)$. This is the $k_f^2$ correction in PESC equations (19), (32)–(35).

The loss function is the integral of absolute sinusoidal current over the intervals that actually switch, normalized to continuous PWM; PESC p. 9, equations (39)–(45). For DPWM0–2 the clamping center is −30°, 0°, +30°. At a fixed carrier, $SLF=1-\cos\delta/2$ for $|\delta|\le60^\circ$, otherwise $SLF=(\sqrt3/2)\sin|\delta|$, where $\delta$ is load angle minus clamping-center angle. The separate DPWM3 expression follows equation (45). Relative loss on the selected basis is $(f_c/f_b)SLF$.

Source discrepancy: the APEC author manuscript p. 4 equations (5)–(7) display $\pi M_i/4$ inside the HDF terms. Its modulation-index definition and plotted curves instead agree with $4M_i/\pi$, as explicitly printed in the later PESC equations. This tool uses PESC. A separate time integration of the actual three-phase switched voltage verifies all seven HDF polynomials; no polynomial was adjusted to fit a reference.

Gate commands explicitly hold the upper device OFF at the negative rail and ON at the positive rail, including equality at carrier extrema. A dimensionless tolerance of $10^{-12}$ around ±1 absorbs floating-point roundoff; interior commands use the triangular-carrier comparison.

Space-vector synthesis and carrier equivalence

The amplitude-invariant Clarke convention makes the reference-vector magnitude equal to the phase-voltage peak. The six active states V1…V6 are 100, 110, 010, 011, 001, 101 at angles 0°, 60°, …, 300°, each with magnitude $2V_{dc}/3$; V0 = 000 and V7 = 111 both give zero load voltage. With wrapped angle $\theta$, sector $k=1+\lfloor\theta/60^\circ\rfloor$ and local angle $\alpha=\theta-60^\circ(k-1)$, volt-second balance gives

Here $T_0$ is the combined zero-state time, unlike sources that call the individual 000 share T0. Conventional SVPWM allocates half of this combined time to each zero vector. The displayed seven segments are $000,F,S,111,S,F,000$, with durations $T_0/4,T_F/2,T_S/2,T_0/2,T_S/2,T_F/2,T_0/4$. In odd sectors F is the lower active vector; in even sectors F is the upper one. This order changes one leg at each transition. Zero-duration segments are allowed at boundaries.

Integrating these states gives the three phase duties independently of the carrier implementation. The table compares them with $d_x=[1+r_x-(r_{max}+r_{min})/2]/2$. Equal zero-state sharing yields the same result: symmetric SVPWM is sinusoidal PWM plus min-max zero-sequence injection. The sequence starts at 000; the existing triangular carrier starts at its minimum, so the sequence cursor includes a half-period shift.

The largest circular reference that fits inside the hexagon is $V_{dc}/\sqrt3$, versus $V_{dc}/2$ for SPWM. The gain is $2/\sqrt3-1=15.47\%$. DUTH course notes, attached PDF pp. 16–23, give the state map, volt-second derivation and range comparison; Imperix TN146 explains min-max equivalence. Van der Broeck, Skudelny and Stanke (1988) is cited as the original journal reference, DOI 10.1109/28.87265; its paywalled text is not used. The state integration, residuals and original drawings are derived here from these equations.

For drawing the exact gate traces, segments shorter than $10^{-13}T_s$ are treated as floating-point zero and omitted from the plotted trace. This prevents a zero-duration 000 or 111 entry from drawing a false OFF/ON spike when a phase is continuously clamped at the maximum linear demand. The dwell table and voltage/duty integrations retain the unrounded fractions.

The frozen phase B gate chart uses exact triangular-carrier crossings rather than sampled gate values. For a carrier starting at −1 and peaking at half a period, the upper gate is ON over $[0,d_b/2)$ and $[1-d_b/2,1]$ in normalized time. At duty zero or one, the trace is constant. Its piecewise-constant area over one period equals $d_b$; checks verify this for every modulation method and near clamping. The displayed duties use the same $10^{-12}$ reference-rail tolerance as the live comparator.

• Balanced three-phase voltage references and approximately sinusoidal fundamental currents; isolated load neutral with no zero-sequence current path.
• Ideal two-level inverter, symmetric triangular carrier, complementary gate commands, and no dead time or minimum pulse width.
• Load high-frequency impedance is represented by the specified per-phase transient/leakage inductance.
• The base carrier/fundamental frequency ratio exceeds 20 for every method in the comparison, following PESC p. 5. Carrier detail uses locally constant references.
• Switching energy is proportional to current magnitude; only relative commutation loss is modeled. The loss reduction is not a total efficiency gain.
• Voltage and current are independent specified operating-point quantities; no load resistance, back EMF or motor current-control loop is solved.
• The comparison covers THIPWM1/6; THIPWM1/4 and adaptive GDPWM are outside the selectable set.
• The reference angle is measured counterclockwise from the phase A / alpha axis (cosine convention). The vector magnitude is the phase-voltage peak.
• Both space-vector scenes and the duty-equivalence table always use conventional SVPWM at the current voltage and actual carrier frequency. Their equal 000/111 split and seven-segment pattern do not describe DPWM, SPWM or THIPWM when those methods are selected.

Use only the linear modulation region: $0<M_i\le\pi/4$ for SPWM and $0<M_i\le\pi/(2\sqrt3)$ for the other six methods. The HDF chart stops SPWM at its own limit. Signed current angle is limited to −90°…+90°; power factor is displacement factor, not true power factor including harmonics.

The ripple approximation is intended for high carrier ratios and predominantly inductive switching-frequency impedance. If estimated ripple exceeds 20% of fundamental current, a warning asks for better operating-point data or a more suitable inductance/frequency; the sinusoidal-current loss assumption becomes less reliable.

Playback is slowed for learning; the displayed frequency values remain the physical operating frequencies. Only the angle, local comparator, duties and drawing change each frame. No device loss in watts, individual harmonic spectrum, peak ripple, common-mode voltage, overmodulation, dead time, pulse suppression, semiconductor conduction loss or thermal model is included.

Above $V_{ph,pk}=V_{dc}/\sqrt3$, a circular reference leaves the hexagon during part of the cycle. Dwell-time saturation and the transition toward six-step operation require an overmodulation algorithm; amplitude gain becomes nonlinear and low-order distortion grows. This tool rejects that region instead of silently clipping. At the linear limit or a sector boundary, some seven-segment durations are zero and the number of distinct physical transitions is reduced.