Dual Active Bridge Calculator: Power, ZVS and RMS Currents

Let n = N₁/N₂, Vᵣ = nV₂, f be the per-device repetition frequency, and s = θ/360° the signed outer displacement in full periods. Total L is primary-referred. Positive P flows from bridge 1 to bridge 2.

SPS power and sizing

For two bipolar bridges,

The lower solution |s| ≤ 1/4 is inverted analytically for a power target; the same equation gives L at an entered nonzero phase. See Krismer, attached thesis pp. 73–76 (printed pp. 57–60), and imperix TN115. The rationalized inverse avoids cancellation near zero power.

All four modulation modes

Each leg has 50% gate duty. A bridge with pulse fraction D has leg rising edges a = (1−D)/4 and b = (1+D)/4; the negative pulse follows half a cycle later. The secondary edges are delayed by s. Thus each active pulse lasts DT/2. SPS: Dp = Ds = 1; EPS: Dp adjustable, Ds = 1; DPS: Dp = Ds adjustable; TPS: independent Dp and Ds. These are pulse-centred conventions; translate other publications’ edge-based shifts before comparing them.

Kirchhoff’s law L di/dt = v₁ − nv₂ is integrated on every constant-voltage interval, using the zero-mean, half-wave-antisymmetric steady-state solution. For interval fraction Δu and endpoint currents iₐ, iᵦ, its contributions are Δu(iₐ+iᵦ)/2 to mean current and Δu(iₐ²+iₐiᵦ+iᵦ²)/3 to mean-square current. Power uses the interval voltage times its mean-current contribution. No time-stepping approximation enters power, peak or RMS results. The waveforms and quadrature implement the interval method in Krismer pp. 73–74. Secondary current magnitude is n times primary current. Each MOSFET position carries I_RMS/√2, counting forward and reverse channel conduction; parallel chips share this only if the layout and devices support it.

ZVS boundaries and screen

Favourable commutation currents are −i(aₚ), +i(bₚ) on bridge 1 and +ni(aₛ+s), −ni(bₛ+s) on bridge 2. Half-wave symmetry covers the other half cycle. A nonpositive least favourable current fails the ideal polarity test. In SPS, the ideal limits are |θ| > 90° max(0,1−V₁/Vᵣ) on the primary and |θ| > 90° max(0,1−Vᵣ/V₁) on the secondary.

The first-order screen additionally requires current above both 2CossV/t_dead (charge for a two-device leg, current held constant) and 2V√(Coss/L_side) (the conservative stored-energy rule in imperix TN119, attached p. 2). L_side is L or L/n². The larger threshold is subtracted from the least favourable commutation current. The SPS screening angles solve these linear current inequalities; a threshold beyond 90° is unreachable on this branch. Minimum screened SPS power is a boundary estimate; strict positive margin is required. The general-mode chart recalculates every leg edge as outer phase changes.

Part sizing hints

Inductor peak energy is LI_peak²/2. External primary-referred inductance is L minus measured leakage. With all series inductance ahead of the ideal transformer, secondary bridge voltage sets core flux: N₂ ≥ V₂Ds/(4fB_peakA_core). Primary turns are nN₂ before integer reconciliation. Copper area is winding RMS current divided by chosen current density. These are starting constraints, not a complete magnetic or thermal design.

Ideal full bridges, stiff DC buses, lossless transformer with n = N₁/N₂, constant total transfer inductance, negligible magnetizing current and symmetric 50% leg gating. The chosen steady-state current has zero DC component; startup and transient offsets are excluded. All primary currents also pass through the lumped series inductor; secondary current magnitude is n times larger.

Power and RMS current use instantaneous ideal transitions. Dead time and switch output capacitance affect only the explicitly labelled ZVS screen; they do not reshape the computed steady-state waveform. Coss is one effective constant value per switch position, including parallel devices and added capacitance. The energy and charge screens use that same value; a nonlinear device generally requires separate charge-equivalent and energy-equivalent capacitances or its Qoss/Eoss curves.

The interval integrals, pulse-centred timing representation, commutation sign tests and magnetic hints are derived here from circuit laws. The SPS power equation and independent RMS examples follow the cited sources. The 2022 Chen paper motivates the light-load ZVS/RMS tradeoff; its coupled-inductor ISOP half-bridge hardware and hybrid controller are not represented by this ordinary full-bridge model.

Use the ±90° outer-phase branch and pulse fractions from 0.02 to 1. The phase and inductance solvers apply to SPS only. EPS, DPS and TPS evaluate the selected timing without finding an optimum or enforcing a power target. SPS boundary and maximum-power results remain explicitly labelled SPS comparisons when another mode is selected.

A screening pass is not a guaranteed ZVS result. Resonant commutation, concurrent transitions, changing current during dead time, excessive dead time, voltage-dependent capacitance, diode recovery, magnetizing current and layout parasitics can change the boundary. Validate the commutation voltage before turn-on in a switching model and on hardware. The TN119 energy rule is conservative and is not an exact resonant boundary.

MOSFET RMS values count reverse channel current over the full switching period, ignore dead-time diode intervals and are per switch position. For IGBTs, split transistor and antiparallel-diode current separately. DC capacitor RMS assumes an external source or load carrying only the average DC current; filter impedance changes current sharing.

The magnetic hint assumes L is lumped entirely before the transformer; another leakage distribution changes actual core volt-seconds. Choose an integer turns pair, re-enter its ratio, and verify saturation, core loss, copper AC loss, window fill, cooling and insulation. No efficiency, thermal, startup, control-loop, EMI or insulation certification is provided.