Current-Mode Control: Slope Compensation & Type-II Design

Current ramp and sampling

All slopes are voltages at the PWM comparator. With $D'=1-D$, $S_n=R_i V_{on}/L$ and $S_f=R_i V_{off}/L$, the cycle perturbation multiplier is $\lambda=(S_e-S_f)/(S_n+S_e)$. Stability requires $|\lambda|<1$; a positive minimum slope boundary must be strictly exceeded.

Ridley's public modeling article (attached s1, pp. 4–6) supplies the enhanced current-source response:

Here $\omega_n=\pi f_s$, $m_c=1+S_e/S_n$ and $Q_p^{-1}=\pi(m_cD'-1/2)$. Solving for a target Q gives the nonnegative artificial slope ratio. Negative Q denotes an unstable inner loop; Q is undefined at the boundary.

Topology and gain

The load-pole factor is $a=1+\delta_b$ for buck, 2 for boost, and $1+D$ for flyback, with $\delta_b=(RT_s/L)(m_cD'-1/2)$ and $\omega_p=a/(RC)$. Both the buck pole and gain include the ramp correction from Ridley p. 4 and TI SPRABE7A Eqs. (3), (5). The ESR zero is $1/(r_cC)$. The RHP time coefficient is zero for buck, $L/(RD'^2)$ for boost, and $n^2DL_p/(RD'^2)$ for flyback, with $n=N_s/N_p$.

The DC gains used are $R/[R_i(1+\delta_b)]$, $RD'/(2R_i)$ and $RD'/[n(1+D)R_i]$. These follow by linearizing the ideal CCM power balance at fixed averaged current command. TI SLYT511, p. 15, independently gives the boost factor of one-half. SLVA636 Eq. (6) omits that factor; its RHP-frequency example is used for verification, not its DC gain. ADI's unified-model article supplies topology, sensing and CCM context.

Type-II network

Use $C(s)=K_i(1+s/\omega_z)/[s(1+s/\omega_h)]$. The high-frequency pole is chosen first; the zero phase at crossover is solved for the requested margin. Gain is normalized so $|G_{vc}C|=1$ at the requested crossover. Every sign change in loop magnitude on the 501-point log grid is refined with a root solver. A normalized characteristic polynomial also checks closed-loop stability, including possible crossings beyond the plotted band.

For the voltage-op-amp network, $C_\Sigma=1/(R_1K_i)$, $C_3=C_\Sigma f_z/f_h$, $C_1=C_\Sigma-C_3$ and $R_2=1/(2\pi f_zC_1)$. These exact impedance relations retain both capacitors, as in SLVA662 Eq. (4), rather than assuming $C_3\ll C_1$.

Load-step estimate

The reduced disturbance model is $Z_o(s)=(R/a)(1+s/\omega_{ESR})/(1+s/\omega_p)$. The plotted change is the inverse Laplace transform of $-\Delta I\,Z_o/[s(1+G_{vc}C)]$, evaluated by polynomial poles and residues. An unstable pole suppresses the trace. The plot keeps 401 uniformly spaced points through $1/f_c$ and adds 301 geometrically spaced points through the full horizon. With $\sigma=-2\pi f_n\max\Re(p_j)$, the remaining tail is bounded by $\Delta I\sum|r_j|e^{-\sigma t}$. The horizon is at least $8/f_c$ and extends until that envelope falls below 0.1% of the fine early-window excursion. A cap of $10000/f_c$ prevents impractically long windows; hitting it produces an explicit truncation warning. The separate early-time plot keeps the ESR jump and dip readable. This output-impedance approximation is derived here; it is not a measured transient or ADI's full switch model.

Approximation screening

The remaining low-frequency approximation is screened at a fixed 10% correction limit; this is a screening threshold, not a guaranteed total model-error bound. For boost and flyback, linearize the actual steady-state peak command

At fixed input voltage and external ramp slope, its DC-gain denominator correction relative to the ideal current-source gain is

where $(a_0,n)=(2,1)$ for boost and $(1+D,N_s/N_p)$ for flyback. The simplified gain overestimates the averaged peak-command gain by the ratio $\eta_g$.

Eliminating duty perturbations from the averaged inductor and output equations gives a low-frequency denominator with constant term $(a_0/R)(1+\eta_g)$, linear term $C+t_i/R$ and quadratic term $Ct_i$, with $t_i=T_sD'(k+1/2)$. The first-order pole shift indicator is $\eta_p=|(1+\eta_g)/(1+t_i/(RC))-1|$. Warn when either $\eta_g$ or $\eta_p$ exceeds 0.1. These screening relations are derived here for ideal CCM, and do not replace the sampled-data model. For the corrected buck, screen the remaining time-coefficient ratio $t_i/(RC)$ instead. All topologies also require separation of the dominant pole below $f_s/20$, small ESR relative to load, and a moderate artificial ramp.

• Ideal, fixed-frequency, trailing-edge peak-current control in CCM with a positive resistive incremental load. No losses, propagation delay, current-sense filtering, slope curvature, transformer leakage or extra isolation-loop poles.
• Flyback $L_p$, ripple and sense gain refer to primary magnetizing current. $n=N_s/N_p$; output capacitance and ESR remain secondary-side quantities.
• The buck model includes the ramp-dependent DC gain and dominant pole. Boost and flyback retain the enhanced current-source approximation, with explicit 10% omitted-correction screening. Very steep ramps or a dominant pole approaching the sampling poles require a full switch model.
• The Type-II result is the complete AC feedback transfer from output voltage to control voltage for the drawn voltage op amp. Do not multiply a separate feedback-divider ratio into it. Amplifier gain-bandwidth, control-voltage range and the lower DC divider resistor must be checked separately.
• All engineering calculations are independent of the animation input; play only updates the cursor and its drawing.

Use for nominal CCM loop design and education, with $0.02<D<0.95$, positive current valley, crossover below $f_s/10$ and, for boost/flyback, below $f_{RHP}/5$. The frequency model is evaluated only through $f_s/2$. A finite grid can miss very narrow features; inspect peaking and verify the measured loop. A positive first-crossing phase margin alone does not establish stability.

The load step is a reduced linear estimate. Prefer $\Delta I\leq20\%$ of nominal load and predicted voltage movement below 10%; details within the first ten switching cycles are not switching-level predictions. The first point represents the instantaneous ESR drop. The early-time detail uses 401 points through one crossover period; the full chart adds logarithmically spaced tail samples. The displayed settling assessment reports whether the 0.1% modal envelope was captured or the plot was truncated at its time cap. No transient is shown when the characteristic polynomial predicts instability.

DCM has different power-stage dynamics and does not share this CCM subharmonic criterion. Constant on-time, valley current mode, multiphase control, current limits, discontinuous pulse skipping, OTA/opto feedback and constant-power loads are outside scope. Recheck line, load, capacitance derating, ESR, inductance, sensing gain and component tolerances.

The implementation uses open public restatements. A direct cross-check against the original 1991 IEEE paper remains pending IEEE Xplore access.

When the inner current loop is unstable or marginal, Bode gain/phase traces and phase-margin results are withheld; increase the artificial ramp first. The Type-II circuit shows Rb for DC setpoint biasing only; its value follows the controller reference and desired output voltage.