Solid-State Transformer: MV to 800 V DC, Modules and Efficiency

This is a three-phase star-connected input-series output-parallel (ISOP) SST. Each cell contains a cascaded H-bridge (CHB) active rectifier, a floating DC link, and an isolated single-phase-shift (SPS) dual active bridge. Huber and Kolar (2016), attached pp. 5–9, describe the modular and isolation concepts; this loss implementation is derived here.

Series sizing. The upper-tolerance peak phase voltage is $V_{LL}\sqrt{2/3}(1+g)$. The allowable cell link is the smaller of the vendor-qualified cosmic-ray voltage ceiling and the transient blocking ceiling $V_{DS}/k_{os}$. Required active cells are the largest of the voltage count, rated-power count and architecture floor. Add the redundant cells. The DC-link setpoint and transformer hardware are sized for the required count after all reserved bypasses; healthy hot redundant cells share power at that same setpoint.

DAB solution. Leakage inductance is designed for the entered cell rating and rated phase shift. Integer primary turns meet the flux limit; integer secondary turns set the actual conversion ratio. The low-phase-shift root of $P=V_1 nV_2\delta(1-\delta/\pi)/(2\pi fL)$ gives the commutation currents and exact piecewise-linear leakage RMS current. A fixed-point iteration includes secondary winding, channel and switching losses in the transferred power. Dead-time diode loss replaces the corresponding channel-conduction estimate. Primary RMS current includes magnetizing-current harmonics. A quadratic predictor and fixed-point correction close the grid-current-dependent front-end losses.

Semiconductors. Channel loss uses two conducting switch banks and linearly interpolated hot Rds,on. Overlap switching energies scale with voltage and current. Coss energy Eoss(V) and charge Qoss(V) are stored separately and evaluated at the operating voltage with an energy-consistent power-law capacitance fit. ZVS needs the right current polarity, sufficient charge transfer during dead time, and sufficient inductive commutation energy. The charge condition is I·t_dead ≥ 2·N_parallel·Qoss(V); the energy condition is L·I² ≥ 4·N_parallel·Eoss(V), with the required current polarity. Residual turn-on Coss energy follows Eoss(V) and the overlap term follows residual voltage; turn-off loss remains. Each full bridge has four diode intervals per period. Their diode loss replaces the channel conduction already counted in the same intervals. This is an energy/charge commutation model, not a transient SPICE simulation. TI TIDUES0E (2024), sections 2.3.4–2.3.5, provides the SPS and loss-model basis.

Magnetics. The N87 sinusoidal Steinmetz fit uses TDK June 2025 p. 2: the 25/100 kHz points determine the frequency exponent, and the 100/300 kHz points determine the flux exponent. iGSE normalizes that fit by the sinusoidal derivative integral and integrates the triangular flux of a 50% duty full bridge. Each retained odd current harmonic is weighted by its Dowell resistance factor at winding temperature. Interleaved sections reset the ideal one-dimensional MMF. The exact RMS tail is retained at DC resistance.

Isolation and comparison. The highest floating primary is assessed against the full phase-to-earth peak plus local half-link and half-output excursions. Barrier thickness is the larger of working-field and allocated-impulse requirements. A parallel-plate capacitance gives LF and finite-rise-time HF dielectric losses. Conventional input power is worked backwards through DC/DC, rectifier, and an LFT with fixed iron and current-squared copper loss; auxiliaries are included in both paths.

Sweep validity. Every plotted SST point independently tests DAB transfer capacity, grid-input feasibility, loss-iteration residual, bypass budget and semiconductor voltage limits. Infeasible points are gaps in the efficiency and both commutation curves. The conventional curve retains its own full load range. Vector power-balance properties check every retained point, including the review stress case.

Reference scope. The Enphase case is explicitly an architecture fixture. Independent voltage-count cases use Huber and Kolar (JESTPE 2017), Table I: the published 10 kV grid, M=0.8 and 50–60% blocking utilization imply 15, 11 and six cells for 1.2, 1.7 and 3.3 kV devices. Power and architecture floors remain below those counts. These references validate stacking, not the paper's IGBT losses against this SiC model.

Balanced sinusoidal grid currents at unity power factor; equal voltage/power sharing; stiff cell links; hot redundancy; de-energized bypassed cells; no reverse power. All three phases have the same bypass count. Rated cell power is a user-imposed output limit.

The sweep compares specific example parts, not intrinsic voltage-class merit: C3M0032120K Rev. 6 (2024), C2M0045170D Rev. 3 (2024), CAB5R0A23GM4 Rev. 3 (2025), and preliminary IBB020A33GM4 Rev. 1 (May 2026). The same secondary choice and switch-bank counts are used for every primary option. A “parallel primary position” means a parallel device or module switch position, not a parallel SST cell. Primary CHB and DAB bridges use the same part. Device sizes and generations differ.

Rds,on endpoints are taken from the respective datasheets; the 1.7 kV part's current edition lists a 40 mΩ typical value despite its part-number suffix. Switching uses hot body-diode commutation data; for the 2.3/3.3 kV modules, listed reverse-recovery energy is added to listed turn-on energy. For C2M0045170D, independent reference data are Eoss=139 μJ and Qoss=255 pF×1200 V=306 nC at 1200 V. For C3M0032120K, Eoss=76 μJ and differential Coss=129 pF at 1000 V define a single power-law C(V) fit; its inferred Qoss is a model estimate, not a measured manufacturer charge curve. For 2.3/3.3 kV modules, independent energy and charge allowances multiply tabulated high-voltage Coss. With reference E and Q, Q(V)=Qref·(V/Vref)^b and E(V)=Eref·(V/Vref)^(b+1), where b=Eref/(Qref·Vref−Eref); thus dE=V·dQ. Replace the inferred charge/energy curves with measured data for a detailed design. The 1.2 kV switching data are at 175 °C; their use down to 25 °C is a conservative scenario assumption. Control/gate power, cooling, foil geometry, isolation fields, loss tangent and conventional-path efficiencies are editable engineering assumptions, not vendor promises.

The default 70% primary and secondary blocking fractions are design assumptions, not measured SiC cosmic-ray qualifications. Replace each with a vendor-qualified ceiling at the desired FIT rate, altitude, die area, temperature and off-state duty. No universal SiC derating law or numerical FIT prediction is claimed. Infineon's cosmic-radiation guidance explains why those conditions matter.

Use for steady-state architecture and loss tradeoffs, not protection or insulation certification. The efficiency verdict is conditional on the named devices and entered loss parameters; no measured end-to-end CHB–DAB SST benchmark is available here. Enphase's 27 October 2026 result uses GaN and a proprietary stage: 44 cells per phase and 132 total are an architecture fixture only, not an independent sizing reference. Its release does not report measured efficiency. OCP SST v0.3 (2026) gives a ≥98% power-train target, excluding auxiliary accounting used here.

N87 loss parameters represent a local fit around 100 °C and roughly 25–100 kHz, 0.1–0.2 T; other conditions extrapolate it. The core temperature is fixed at 100 °C for that material fit. Winding temperature is independent. No DC flux bias, minor flux loops, fringing, 2D proximity field, foil-edge current crowding, capacitor ESR, DC-link ripple, busbar/contact loss, detailed cooling model, semiconductor SOA or transient stability is solved. Rectifier and conventional DC/DC efficiencies are held constant across the displayed load range; substitute measured load-dependent losses for procurement comparisons.

The default spectrum retains 401 odd harmonics (through the 801st); the convergence check doubles resolution. Omitted winding harmonics use DC resistance for their exact RMS-current tail, so their small excess AC resistance is omitted. The finite-rise-time dielectric spectrum uses the same cutoff and may require more terms for very fast edges. The 81-point load curves are calculated directly. Gaps mark points failing the operating feasibility tests; a feasible selected load does not imply feasibility over the full displayed load range.

The insulation field method sizes a uniform solid barrier only. It does not calculate air clearance, creepage, partial discharge, triple points, surface contamination, lifetime or surge coordination. The full allocated impulse is applied to each MF barrier unless the designer supplies another coordinated allocation. Check insulation and installation against the standards in force. A semiconductor module's case isolation rating is not the MF transformer isolation requirement.