Flying Capacitor Inverter Sizing and Natural Balancing — 800 V

Size the flying capacitor of a three-level inverter, predict natural balancing from switching harmonics and load impedance, and animate phase-shifted PWM.

#FCML #Floquet analysis #flying capacitor #natural balancing #phase-shifted PWM #SIC

A three-level flying capacitor inverter creates an intermediate switching level without a separate isolated supply. On an 800 V DC link, its flying capacitor normally sits at 400 V, allowing each device to block approximately half the bus voltage. The capacitor must carry alternating cell current, hold its voltage ripple within the design limit, and recover from imbalance quickly enough for the application.

This flying capacitor sizing calculator is for engineers comparing capacitor banks, students studying phase-shifted PWM, and designers assessing whether natural balancing is sufficient. It treats one inverter leg with two complementary switching cells and carriers shifted by 180°. The default case represents an 800 V SiC design with a 40 kHz switching frequency per cell.

Start with the DC-link voltage, switching frequency, modulation index and expected peak phase current. Set the current lag angle to represent the operating point. Enter the installed nominal capacitance and the minimum fraction that remains after tolerance, DC bias and temperature. The ripple limit applies to the capacitor's terminal voltage, including ESR. Compare the calculated minimum nominal capacitance with the installed bank, then check its RMS-current capability and ESR dissipation separately.

Natural balancing is driven by the dissipative part of the load admittance at switching harmonics. Enter a series RL impedance appropriate to those frequencies. For a frequency-dependent load, add the series-connected parallel RL branch and fit its parameters to impedance measurements. A motor's nameplate resistance and fundamental power factor do not characterize this response. The harmonic chart shows which carrier groups supply the balancing action.

The transient plot compares the selected capacitance with half and twice that value. In the harmonic model, more capacitance reduces ripple and slows voltage recovery. Fixed-duty comparisons recompute the switched model, whose damping need not vary monotonically with capacitance. The target time describes reduction of the mean imbalance, rather than disappearance of switching ripple. A lossless inductive load provides no dissipative self-balancing in this averaged model.

Use the play control to follow the switching states and capacitor current over one cell switching period. In sinusoidal mode, the selected fundamental angle freezes the reference and phase current for that short interval. Fixed-duty mode solves the coupled RL–capacitor switching equations, including capacitor ESR. It searches candidate capacitances, verifies the recommendation by substitution, and obtains the periodic orbit and its decay from the cycle transition matrix. Its load returns to DC−; the sinusoidal switching voltage is referred to the DC midpoint.

The tool does not design precharge, active balancing, dead-time compensation, gate timing, protection, insulation or a three-phase floating-neutral network. The switch-voltage result includes the entered overshoot allowance; it does not calculate SiC commutation ringing. Choose capacitor voltage ratings from the calculated stress and the manufacturer's derating guidance. Verify startup, fault behavior and the measured harmonic impedance before committing a hardware design.

How it is calculated

For each cell, s1,s2s_1,s_2 are 0/1 switching functions. With e=vC−Vdc/2e=v_C-V_{dc}/2 and d=s1−s2d=s_1-s_2, Kirchhoff's equations give iC=dii_C=d i and vo=Vdc(s1+s2−1)/2−dev_o=V_{dc}(s_1+s_2-1)/2-d e for a midpoint-referenced load. Equal duty and a 180° carrier shift generate alternating capacitor charge and discharge intervals.

For a locally constant current, the longest charging interval is aTsaT_s, where a=min⁡(D,1−D)a=\min(D,1-D). Therefore ΔvC,pp=∣i∣a/(fsC)\Delta v_{C,pp}=|i|a/(f_s C) and the terminal-ripple bound adds 2∣i∣RESR2|i|R_{ESR}. A 1,441-point fundamental sweep finds the required effective capacitance for the specified sinusoidal current and ripple budget. Divide by the minimum capacitance fraction to obtain nominal capacitance. The separate all-duty frozen-current estimate uses a=1/2a=1/2, equivalent to C≥Ipk/(2fsΔv)C\ge I_{pk}/(2f_s\Delta v) before ESR and derating. This comparison assumes prescribed current; it does not size the coupled fixed-duty circuit. RMS capacitor current follows ⟨iC2⟩=⟨2ai2⟩\langle i_C^2\rangle=\langle2a i^2\rangle.

Natural balancing follows the switching-function harmonic framework of Wilkinson et al. (2006) and McGrath and Holmes (2009), adapted here to one leg with the entered load impedance. For the 32 odd carrier groups through order 63, m=1,3,…,63m=1,3,\ldots,63, the carrier coefficient is dm(θ)=2sin⁡[mπD(θ)]/(mπ)d_m(\theta)=2\sin[m\pi D(\theta)]/(m\pi). A 256-point FFT gives its fundamental sidebands dmnd_{mn}. The model evaluates the load at every retained frequency mfs+nf0mf_s+nf_0, rather than only at fsf_s. With both frequency signs included, Gb=∑m,n∣dmn∣2ℜ{Y(mωs+nω0)}G_b=\sum_{m,n}|d_{mn}|^2\Re\{Y(m\omega_s+n\omega_0)\}, Ce˙=−GbeC\dot e=-G_b e, and τ=C/Gb\tau=C/G_b. The optional impedance is Z(s)=R+sL+(RpsLp)/(Rp+sLp)Z(s)=R+sL+(R_p sL_p)/(R_p+sL_p).

Fixed-duty mode also solves the full switched equations Li˙=vdc(s1+s2)/2−de−(R+d2RESR)iL\dot i=v_{dc}(s_1+s_2)/2-d e-(R+d^2R_{ESR})i and Ce˙=diC\dot e=d i. Exact matrix exponentials are composed at the PWM edges. Half-cycle symmetry, i(t+Ts/2)=i(t)i(t+T_s/2)=i(t) and e(t+Ts/2)=−e(t)e(t+T_s/2)=-e(t), gives the periodic initial state from (J−P1/2)x0=b1/2(J-P_{1/2})x_0=b_{1/2}, avoiding the ill-conditioned full-cycle fixed-point solve. The dominant Floquet multiplier gives τ=−Ts/ln⁡ρ\tau=-T_s/\ln\rho. For real multipliers the small eigenvalue deficit is found from I−MI-M and evaluated with log1p; for a complex-conjugate pair the log modulus follows the exact Liouville determinant. This decay time replaces the harmonic approximation in fixed-duty mode. The periodic current averages are checked against the independent Maple simulations in Kadyrov et al. (2018), attached pp. 12–13.

Fixed-duty capacitance sizing evaluates each candidate with the coupled switched circuit, including its changed current. It brackets and bisects the terminal-ripple limit on the high-capacitance branch, with lower effective capacitance max⁡(0.1 μF kC, [a/(fs)]2/L)\max(0.1\,\mu\mathrm{F}\,k_C,\,[a/(f_s)]^2/L) and an upper nominal limit of 1 F. The branch floor keeps the LC phase during a capacitor conduction interval at or below one radian; a resonant current-collapse solution is not selected as a design. Terminal extrema include switching edges and the stationary points of the damped RLC solutions, rather than only the plotted samples. The required nominal value is rounded upward to 0.01 µF and is re-evaluated by substitution; its predicted ripple is checked against the limit. Fixed-duty comparison curves rebuild the transition matrix for half and twice the capacitance; linear time-constant scaling is used only for the harmonic model.

Assumptions

Two cells, one flying capacitor, complementary ideal switches, equal cell duty ratios and 180° phase-shifted triangular carriers. Sinusoidal mode uses D=(1+Msin⁡θ)/2D=(1+M\sin\theta)/2 and the entered sinusoidal phase current; it allows externally imposed current or back EMF. The harmonic load is linear and passive. The added parallel RL branch is a frequency-response fit, not an identified induction-motor model.

The sinusoidal sizing and switching-period animation freeze phase current within each cell period; include expected switching-current excursions in the peak-current input. The sinusoidal balancing envelope is the slow, small-imbalance harmonic average. Fixed-duty mode instead computes actual coupled current and capacitor-voltage ripple, and sizes a candidate bank with that coupled solution. Its animated orbit is steady state. Initial imbalance sets the recovery envelope and voltage-stress allowance, not that periodic orbit.

Capacitance fraction applies to all calculations. ESR is constant: it contributes terminal ripple and loss, and is included in the exact fixed-duty state equations. It is omitted from the sinusoidal harmonic balancing feedback. The overshoot allowance is supplied independently.

Where it applies

Intended for capacitor selection and natural-balancing assessment of a single three-level leg. The sinusoidal harmonic model retains the 32 odd carrier groups through order 63, with 256 Fourier bins per group (the center and 255 sideband bins); the switching/fundamental ratio must be at least 130 to keep these groups separated. The last eight retained groups are monitored as a truncation indicator, not a rigorous error bound. Very resistive loads may require more orders. The fundamental sizing sweep uses 0.25° spacing. The animation uses 801 samples; fixed-duty orbit waveforms use 80 exact state advances per nonzero PWM interval. The sizing solver includes continuous terminal-voltage extrema even when a waveform sample misses a peak. RMS current and displayed peak-current estimates still use the plotted samples.

Sinusoidal balancing assumes the imbalance changes slowly relative to a fundamental cycle; a warning appears below five fundamental periods per time constant. The exponential curve is a mean-envelope estimate. Fixed-duty decay uses the dominant Floquet multiplier, so an oscillatory transient is represented by its envelope. A log-modulus decrement no greater than 10⁻¹⁰ per cycle is treated as numerically unresolved: the time readouts and affected curves are withheld, a corrective condition is shown, and no negative recovery time is reported. A 70-digit independent evaluation of the review's weak-damping case gives a decrement about 6.23 × 10⁻¹⁶ per cycle, below dependable double-precision resolution. These are not precharge or startup simulations. A purely reactive harmonic load has no finite dissipative balancing time; the plot then retains the initial imbalance.

Check the load impedance over the relevant switching-frequency range, including winding resistance, skin/proximity effects and any external filter. A single-leg impedance is not automatically the transfer impedance of a three-phase floating-star load. The 2009 motor identification procedure and its experimental motor parameters are not reproduced here.

Switch stress is bounded by Vdc/2+∣e0∣+Δvterminal,pp/2+VspikeV_{dc}/2+|e_0|+\Delta v_{terminal,pp}/2+V_{spike}. This assumes a centered ripple and ideal complementary operation; it excludes bus transients, dead time, unequal gate delays, parasitic LC ringing and faults. Capacitor RMS rating, dielectric derating and thermal behavior must be checked with component data. Natural balancing does not establish a safe initial capacitor voltage before switching.

Fixed-duty sizing returns a verified point on the stated high-capacitance branch within 0.1 µF to 1 F nominal, rather than a global minimum across resonant branches. The all-duty frozen-current estimate is only a comparison for the current of the installed bank. The capacitor chart shows ripple versus fundamental angle in sinusoidal mode and the exact dielectric/terminal voltage versus switching time in fixed-duty mode. The switching-period lanes have separate physical A/V scales, with the capacitor DC reference printed on its voltage axis.

References

  • R. H. Wilkinson, T. A. Meynard and H. du Toit Mouton, Natural Balance of Multicell Converters: The Two-Cell Case, IEEE TPEL 21(6), 1649–1657 (2006). https://doi.org/10.1109/TPEL.2006.882958 ; open repository: https://digitalknowledge.cput.ac.za/handle/11189/1768
  • B. P. McGrath and D. G. Holmes, Natural Capacitor Voltage Balancing for a Flying Capacitor Converter Induction Motor Drive, IEEE TPEL 24(6), 1554–1561 (2009). https://doi.org/10.1109/TPEL.2009.2016567
  • T. A. Meynard and H. Foch, Multi-level conversion: high voltage choppers and voltage-source inverters, PESC 1992, 397–403. https://doi.org/10.1109/PESC.1992.254717
  • S. Kadyrov, P. S. Skrzypacz and Y. L. Familiant, A simple analysis of flying capacitor converter, 2018 author preprint, arXiv:1808.02758v1, pp. 3–7 and 12–13. https://arxiv.org/abs/1808.02758 ; journal DOI https://doi.org/10.1108/COMPEL-07-2017-0282
  • Vincotech, Flying Capacitor Inverter, Rev. 01, §4.3.2, p. 20: capacitance charge/ripple bound and capacitor current requirements. https://www.vincotech.com/fileadmin/user_upload/content_media/documents/pdf/support-documents/reference-design/Vincotech_RD_2021-11_001_v01_3L-FlyingCapacitor.pdf (indexed source; original download was unavailable during build).

Inputs

InputSymbolUnitDefault
Operating waveformwaveformSinusoidal inverter
DC-link voltageV_dcV800
Switching frequency per cellf_swkHz40
Modulation index
Peak sinusoidal reference divided by the triangular carrier peak.
M_pwm0.8
Fundamental frequencyf_lineHz50
Duty ratioD_fixed0.5
Peak phase current
Include the expected operating current; the harmonic load model sets balancing, not fundamental current.
I_peakA40
Current lag angle
Positive means current lags the sinusoidal voltage reference.
lagdeg30
Series load resistance
Use resistance at switching frequencies, including inductor winding loss.
R_loadohm8
Series load inductanceL_loadmH0.25
Frequency dependenceload_modelSeries RL
Parallel-branch resistanceR_skinohm4
Parallel-branch inductance
The R ∥ L branch is in series with the main RL load; fit it to measured impedance.
L_skinmH0.05
Installed nominal capacitanceC_nomuF100
Minimum capacitance fraction
Effective capacitance divided by nominal after tolerance, bias and temperature.
k_C0.8
Capacitor ESRESR_capmohm2
Allowed terminal ripple, peak to peakripple_limitV8
Initial voltage imbalance
Actual flying-capacitor voltage minus half the DC-link voltage.
e_initialV40
Target residual imbalancee_targetV1
Switch blocking-voltage ratingV_switchV650
Commutation overshoot allowance
Enter a measured or separately estimated overshoot above the quasi-static blocking voltage.
V_spikeV40
Fundamental angle for waveformtheta_viewdeg60
Switching-period positionphase_play0.04

Results

With the default inputs above, the calc gives:

ResultValue
Required nominal capacitance44.45 uF
All-duty frozen-current estimate79.72 uF
Effective installed capacitance80 uF
Worst terminal ripple, peak to peak3.62 V
Required capacitor RMS-current capability18.018 A
Capacitor ESR loss0.649 W
Natural-balancing time constant102.7 ms
Time to target imbalance379 ms
Switch voltage including imbalance and overshoot481.81 V
Switch voltage headroom168.19 V
Peak capacitor terminal voltage441.81 V
Sizing assessmentSizing limits met

Checked against sources

Each case below was calculated by this calc and agrees with the value from its source (within the tolerance where one is shown).

Published switched-circuit average, 125 Hz

Source: Kadyrov, Skrzypacz and Familiant (2018), arXiv:1808.02758v1, Fig. 5 and Table 1. T = 8 ms. Independent Maple switched-ODE simulation; ideal switches and no capacitor ESR.

Inputs: Operating waveform = Fixed duty, RL load to DC−; DC-link voltage = 100 V; Switching frequency per cell = 0.125 kHz; Series load resistance = 2 Ω; Series load inductance = 10 mH; Minimum capacitance fraction = 1; Capacitor ESR = 0 mohm; Initial voltage imbalance = 0 V; the others as above.

ResultSourceThis calc
Exact fixed-duty average load current13.018 A13.018 A
Exact fixed-duty mean capacitor voltage50 V50 V

Published switched-circuit average, 250 Hz

Source: Kadyrov et al. (2018), arXiv:1808.02758v1, Fig. 6 and Table 1, T = 4 ms; independently simulated published mean current.

Inputs: Operating waveform = Fixed duty, RL load to DC−; DC-link voltage = 100 V; Switching frequency per cell = 0.25 kHz; Series load resistance = 2 Ω; Series load inductance = 10 mH; Minimum capacitance fraction = 1; Capacitor ESR = 0 mohm; Initial voltage imbalance = 0 V; the others as above.

ResultSourceThis calc
Exact fixed-duty average load current24.341 A24.341 A
Exact fixed-duty mean capacitor voltage50 V50 V

Published switched-circuit average, 62.5 Hz

Source: Kadyrov et al. (2018), arXiv:1808.02758v1, Table 1, T = 16 ms. This large-ripple ideal-circuit benchmark deliberately lies outside practical 800 V capacitor operation.

Inputs: Operating waveform = Fixed duty, RL load to DC−; DC-link voltage = 100 V; Switching frequency per cell = 0.0625 kHz; Series load resistance = 2 Ω; Series load inductance = 10 mH; Minimum capacitance fraction = 1; Capacitor ESR = 0 mohm; Initial voltage imbalance = 0 V; the others as above.

ResultSourceThis calc
Exact fixed-duty average load current1.826 A1.826 A

Fixed-duty recommendation meets the coupled ripple limit

Source: Independent review case supplied by the user: about 6250 µF gives 8 V for this coupled switched circuit. This is a regression against the review's independent numbers, not a published table. Governing switched formulation: Kadyrov et al. (2018), §2, https://arxiv.org/html/1808.02758v1.

Inputs: Operating waveform = Fixed duty, RL load to DC−; DC-link voltage = 100 V; Switching frequency per cell = 0.25 kHz; Series load resistance = 2 Ω; Series load inductance = 10 mH; Installed nominal capacitance = 10 uF; Minimum capacitance fraction = 1; Capacitor ESR = 0 mohm; Initial voltage imbalance = 0 V; the others as above.

ResultSourceThis calc
Required nominal capacitance6,250 uF6,250 uF
Ripple at recommended fixed-duty capacitance8 V8 V

Fixed-duty half-capacitance decay is recomputed

Source: Independent reviewer values supplied by the user: 3.087 ms at 100 µF and 3.750 ms at 50 µF. These are review regression values, not numbers quoted from the paper. Full switched formulation: Kadyrov et al. (2018), §2, https://arxiv.org/html/1808.02758v1.

Inputs: Operating waveform = Fixed duty, RL load to DC−; DC-link voltage = 100 V; Switching frequency per cell = 0.1 kHz; Series load resistance = 10 Ω; Series load inductance = 10 mH; Minimum capacitance fraction = 1; Duty ratio = 0.2; Capacitor ESR = 0 mohm; Initial voltage imbalance = 0 V; the others as above.

ResultSourceThis calc
Natural-balancing time constant3.087 ms3.087 ms
Decay with half the capacitance0.00375 s0.00375 s

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