Buck-Boost DC-DC Converter Design Tool

Ideal switching waveform

The topology is a non-inverting four-switch stage. Q1/Q2 form the input bridge; Q3/Q4 form the output bridge. In buck operation Q3 stays on while Q1/Q2 switch. In boost operation Q1 stays on while Q3/Q4 switch. TI SLVA535B, sections 2–4, describes this power stage; TI LM5176 Rev D sections 7.3.14 and 8.2.2 give the switching convention and worked design.

Let $L=L_{nom}(1-t_L)$, $f=f_{sw}$, and $d$ denote the rising-current fraction. For automatic buck/boost selection, the ideal CCM values are $d=V_o/V_i$ in buck and $d=1-V_i/V_o$ in boost. The positive and negative inductor voltages are $(V_i-V_o,-V_o)$ in buck and $(V_i,V_i-V_o)$ in boost. Thus $\Delta I=V_+d/(Lf)$. Mean inductor current is $I_o$ in buck and $I_oV_o/V_i$ in boost.

Boundary and discontinuous conduction

The boundary load is $I_b=\Delta I/(2K)$, where $K=\max(1,V_o/V_i)$ for automatic buck/boost selection. If $I_o<I_b$, diode emulation gives $d_1=d\sqrt{I_o/I_b}$, $d_2=V_+d_1/V_-$ and $d_0=1-d_1-d_2$. Valley current is zero; otherwise it is $I_{avg}-\Delta I/2$. Peak current follows from the rising ramp. These DCM equations are derived here from volt-second balance and port charge balance, rather than an efficiency-adjusted duty approximation.

Exact current moments and ripple

For ramp endpoints $a,b$, the ramp mean square is $J=(a^2+ab+b^2)/3$. Then $I_{L,rms}^2=(d_1+d_2)J$. Device RMS currents use their conducting fractions. Capacitor RMS follows $I_C^2=I_{port,rms}^2-I_{DC}^2$.

For a port that conducts during fraction $q$, capacitor charge swing is the integral of positive $i_{port}-I_{DC}$: zero if $b\le I_{DC}$, $q[(a+b)/2-I_{DC}]/f$ if $a\ge I_{DC}$, otherwise $q(b-I_{DC})^2/[2f(b-a)]$. This also covers DCM. Ripple upper estimate is $Q/C+ESR\,\Delta i_{port}$; the peaks need not occur together. Required effective capacitance is $Q/(\Delta V_{budget}-ESR\,\Delta i_{port})$. Input source and load currents are assumed constant over each cycle. These moment and charge expressions are derived here; they reduce to the CCM sizing relations in TI SLVA477 and SLVA372.

The nominal inductance recommendation is the analytical maximum of the ideal CCM buck and boost requirements, divided by $1-t_L$. For automatic PWM, the boost requirement can peak at $V_i=2V_o/3$, not necessarily at minimum input. Other range maxima use 201 evenly spaced samples plus the selected point in rating comparisons.

Optional core loss

Venkatachalam et al. (2002), attached PDF pp.3–6, Eqs.9–10 and 15–17, give iGSE. With a sinusoidal reference $P_r$ at $f_r,B_r$ (peak amplitude), this implementation uses

where $\Delta B=L\Delta I/(NA_e)$ and

Flat zero-current intervals contribute no slope loss. Ideal bypass has zero flux swing. Core loss is $P_vV_e$. No minor-loop separation is needed for this single rise/fall waveform. The normalization fit is valid for $0.5\le\alpha\le3$.

Published checks

TI LM5176 Rev D, PDF pp.22–24, explicitly specifies 6–50 V input, 12 V / 6 A output and 300 kHz. Checks compare its 12.7/2.8 uH target inductances, 6.5/4.3/2.1 A ripple values and 25 mV capacitive ripple. The published 90%-efficiency average/peak currents are not targets for an ideal waveform. SLVA535B Appendix A is not used for numerical validation: its buck duty 0.614 conflicts with Eq.1 (about 0.710 using 93% efficiency) and ideal balance (0.660), and it does not explicitly state a switching frequency. The printed maximum-boost duty expression should use minimum input voltage.

Two-state buck-boost PWM and playback

The optional two-state strategy alternates Q1/Q4 (inductor voltage $+V_i$) with Q2/Q3 (voltage $-V_o$). Volt-second balance gives $d=V_o/(V_i+V_o)$; output charge balance gives $I_{L,avg}=I_o(1+V_o/V_i)$. Replace the current ratio in the boundary expression by $K=1+V_o/V_i$. In DCM the same square-root reduction of $d_1$ applies, $d_2=V_i d_1/V_o$, and both bridges are off in the zero-current interval. Q1/Q4 carry the rising ramp; Q2/Q3 carry the falling ramp. The range inductance requirement increases with input voltage, so its maximum is at the upper input limit. These relations are derived here from Kirchhoff’s laws and balance; TI’s 2020 USB power-delivery webinar describes the traditional two-phase switching sequence. Device numbering differs between that presentation and this drawing: here Q3 is the output high-side device.

Playback uses the exact piecewise-linear sizing waveform. One normalized period runs from 0 to 1, with 1 wrapping to the start. Sizing, loss, sweep and waveform-vertex steps do not read the playing input. Only instantaneous states, captions and drawings update each frame. Orange shows the conducting loop and the synchronized cursors; green device symbols indicate an ON command. Idle pass switches may be commanded on while current is zero. Q2 and Q3 conduct source-to-drain; switch charts show current magnitudes. Switch-node voltages are measured from A/B to ground. During DCM idle the floating-node voltage and ringing are not determined by this ideal model, so voltage traces and their dots stop until the next cycle. Dead time and commutation are instantaneous.

• Fixed frequency, one phase, forward power flow and positive output. Automatic PWM uses pure buck or pure boost switching; the optional two-state strategy switches both bridges.
• Ideal voltage conversion and piecewise linear inductor current; diode emulation prevents reverse current in DCM. At equal voltages automatic PWM uses Q1 and Q3 as an ideal bypass with constant current; two-state PWM continues switching.
• Inductance is constant at the entered effective value. Include hot tolerance and DC-current degradation in the reduction allowance; do not count the same reduction twice.
• All four MOSFETs use the same entered hot resistance. Winding and capacitor ESR losses are evaluated from ideal current moments and do not feed back into duty or current.
• Capacitances are effective values, the upstream source supplies cycle-average input current, and load current is constant over a switching cycle. ESL and interconnect impedance are neglected.
• Magnetic defaults are illustrative user entries, not a material database. Core loss is disabled by default. iGSE is a zero-bias estimate; the Steinmetz fit must match frequency, flux and temperature. No i²GSE DC-bias correction is claimed.
• Linear flux estimates neglect remanence. Peak-flux screening multiplies nominal inductance by the highest current calculated with reduced inductance, a conservative combination within that reduction interval. Positive inductance tolerance, gap fringing and material nonlinearity need separate checks.

Use for preliminary steady-state power-stage sizing, not controller qualification. All electrical inputs must be positive; inductance reduction must remain below 1 and the operating voltage must lie in its sweep range. Invalid voltage ranges and exhausted ESR ripple budgets block result cards with corrective messages.

The interface allows low-voltage supplies through higher-power studies; numeric bounds are not a certification of a device's operating range. Check the selected controller's voltage, frequency, peak/average current-limit definition, minimum on/off time and recommended L/C ranges.

With automatic PWM, a 5% band around equal input and output voltage triggers a transition warning. The 5% is a display heuristic, not a controller specification. The sweep uses the selected ideal PWM strategy; real four-switch transition operation can differ from either choice. Two-state buck-boost is not an automatic blend or a reproduction of an IC's proprietary transition law. Range extrema are sampled except for the analytical inductance recommendation; narrow peaks can be missed.

No startup, load transient, compensation, subharmonic stability, forced CCM with negative current, burst/PFM, reverse power, ZVS, dead-time/body-diode loss, switching/gate/reverse-recovery loss, AC winding loss, EMI or temperature-rise model is included. Conduction loss is a partial estimate, not total loss or efficiency. iGSE excludes DC bias and relaxation; its normalization check does not validate any particular core material or the illustrative data.

Capacitor ripple-current ratings must exceed the calculated RMS values under actual thermal conditions. MOSFET blocking voltages need ringing allowance. Verify the final design using the controller datasheet, switching simulation and bench measurements. Waffler and Kolar's negative-current ZVS modulation is cited as further reading and is not implemented.