ANPC Inverter Loss Balancing and Device Temperatures

The method follows the ANPC redundant-zero-state principle of Brückner, Bernet and Güldner (2005, IEEE Transactions on Industrial Electronics), with current paths checked against Electronics 2025, 14, 2944, pp. 4–7. The predictive temperature minimax controller and numerical implementation here are our own; they are not a reproduction of the paper's controller code.

For voltage-reference angle θ, $i=\sqrt{2}I_{rms}\sin(\theta-\arccos PF)$ and active-level duty $d=m|\sin\theta|$. P conduction uses T1/T2 or D1/D2; N uses T3/T4 or D3/D4. Upper and lower zero paths each contain one transistor and one diode. Duty-weighted $|i|$ and $i^2$ give each chip's conduction loss $V_0(T)|i|+r(T)i^2$.

Each carrier cycle contributes one hard turn-on/turn-off pair and one recovering diode, at half-link voltage. For positive current, P↔OU1 switches T1/D5, P↔OL2 switches T2/D3, N↔OL1 switches T6/D4, and N↔OU2 switches T2/D3. For negative current the pairs are T5/D1, T3/D2, T4/D6 and T3/D2. Other gate changes are treated as soft transitions. Energy scales with current and commutation-voltage ratios raised to the entered exponents, and a linear temperature correction. Eon includes transistor heating associated with recovery; Erec is the diode's own dissipated energy.

Every transistor and diode has four Foster states, $\dot{x}_k=(R_kP(T)-x_k)/\tau_k$, with $T_j=T_c+\sum x_k$. Exponential updates use power at each cell's entering temperature. Four consecutive blocks carry the full 48-pole state and energy accumulators without resetting. Every integration-state hottest-junction value is retained for each schedule; only the circuit animation uses 97 reduced frames. A startup-clustered grid resolves the initial heating, with a quadratic time grid at standstill. Nine bisection iterations solve the convex maximum-of-affine-temperatures sharing problem in each cell.

The main solve uses at least 600 cells and at least 40 cells per electrical cycle, rounded into four equal blocks; its maximum is 1,280 cells. Each sweep point independently uses at least 200 cells and 36 cells per electrical cycle. Since the startup-clustered grid's largest interval is less than $t/(0.9N)$, this guarantees at least 32 samples per cycle at every swept point. Frequency sweeps end at $\min(10\,Hz,20/t_{launch},f_{sw}/40)$ to keep their solve budget bounded. Modulation and power-factor sweeps use the entered frequency.

PWM averaging allowance

The thermal solve gives carrier-averaged temperatures. Require $f_{sw}\tau_{min}\ge40$ and at least 20 carrier cycles, including at standstill. Headroom also subtracts an explicit carrier-scale allowance. For each chip class, bound its maximum carrier heat packet by $Q=P_{cond,max}/f_{sw}+E_{sw,max}$ over the case-to-limit temperature interval. The Foster impulse response starts at $h(0)=\sum R_k/\tau_k$. Let $L<0.85$ be a conservative positive electrothermal feedback gain, ignoring helpful negative temperature coefficients.

Under a per-chip cumulative heat-discrepancy bound of two maximum carrier packets relative to the averaged command, integration by parts with the decreasing Foster impulse response gives $|\Delta T|\le4Qh(0)$. The allowance used for both chip classes is $4\max(Q_T h_T(0),Q_D h_D(0))/(1-L)$. This is an analytical allowance under the stated switching-sequence assumption, not a PWM-resolved waveform. Reported headroom is $T_{limit}-T_{average,peak}-\Delta T_{PWM}$.

Balanced sinusoidal phase-current amplitude, constant frequency, modulation and case temperature throughout the entered launch window. Positive current leaves the phase terminal. The same transistor and diode characteristics apply at all six positions. There is no simultaneous upper/lower zero-path conduction.

Default electrical data are approximate straight-line on-state fits anchored at 300 A: VCE=1.76/2.00 V and VF=1.65/1.65 V at 25/125 °C. Switching energies use Infineon FF300R12ME4 revision 1.10 (2025), pp. 4–6, at 300 A, 600 V and ±15 V gate drive, external gate resistance 1.3 Ω. Temperature coefficients interpolate the 25 and 125 °C anchors linearly; they extrapolate above 125 °C. These fits do not digitize the complete nonlinear datasheet curves.

The Foster shape uses revision 3.1 (2013), pp. 6–7: resistance fractions 0.06, 0.33, 0.32, 0.29, time constants 0.01, 0.02, 0.05, 0.1 s, total IGBT/diode resistances 0.097/0.15 K/W. The later 2025 table lists 0.094 K/W for the IGBT; this model deliberately retains the older published Foster fit rather than silently renormalizing it. Replace the parameters for the actual module revision. Initial junction rise is distributed among poles in proportion to their resistances.

Use linear SPWM, 0≤m≤1, with at least 40 carrier periods per electrical cycle. Carrier averaging additionally requires at least 40 carrier periods within every Foster time constant and at least 20 carrier cycles in the launch window. These are enforced even at zero output frequency. Fast poles or short windows outside this domain require a PWM-resolved thermal model; an averaged headroom must not be used there.

The PWM allowance assumes evenly interleaved complete cycles with cumulative per-chip heat error no larger than two worst-case carrier heat packets relative to the commanded average. Verify that bound in the realized modulation sequence; simple long batches of native and opposite paths do not satisfy this assumption. The allowance covers carrier-scale conduction and switching heating plus bounded pulse-density quantization through the stated Foster/linear-feedback model. It does not cover unmodeled commutation energy, gate-timing errors, neutral-point imbalance, overvoltage or semiconductor safe operating area.

The main waveform keeps every integration sample, including all local peaks; no decimation or PCHIP reconstruction is used for the launch chart. Only the circuit animation interpolates 97 frames. Main grids start at 600 cells and grow to at most 1,280; longer/higher-frequency windows beyond that resolution budget are rejected. Sweep resolution is chosen separately at every point, and the frequency range is shortened to at most 20 cycles per window and the carrier-frequency limit. The maximum phase increment is checked across all sweep points. PCHIP interpolation is used only between the nine modulation/factor points or ten frequency points.

The 25–125 °C electrical anchors are approximate fits; their linear temperature slopes extrapolate above 125 °C. Carrier-averaged temperatures above 150 °C in a comparison or sweep indicate an overload region, with extrapolated numerical values. The initial module's thermal fit and electrical data come from different published editions as stated in Assumptions.

This remains a phase-leg comparison with a held case boundary. For standstill or partial cycles, calculate all three initial phase angles separately and retain the worst junction temperature; no three-phase dissipation total is reported. Cooler transients, extra fundamental-frequency/path-transfer energies, dead-time losses and gate-drive/output-capacitance losses are excluded. Independent device anchors and numerical regression checks are available, but no independent measured complete ANPC launch-temperature dataset is available here.