Op-Amp Gain and Bandwidth Calculator

Resistive gains follow the ideal op-amp node equations in TI Op Amps for Everyone, chapter 3: equal input voltages and no signal current into the pins. With $k=R_f/R_1$, the inverting gain is $-k$, non-inverting gain is $1+k$, matched difference gain is $k$ applied to $V_2-V_1$, and the summer is $-R_f(V_1/R_1+V_2/R_2)$. Difference mode fixes $R_3=R_1$ and $R_4=R_f$ with the divider returned to ground. Summer inputs share one frequency; their signed phasors add before amplitude and phase are extracted.

Set the signal sources to zero to find noise gain: $N=1+R_f/R_1$, with $R_f/R_2$ added for the summer. The dominant-pole approximation gives $f_c=GBW/N$ and $H(f)=1/(1+jf/f_c)$. The Bode magnitude is for the primary input; the phase chart shows the additional pole lag. Inverting polarity adds 180° separately. TI SBOA270C and SBOA271A, design steps on p. 2, provide independent worked checks.

For sine peak $V_p$, the required slew rate is $2\pi fV_p$ and the full-power frequency is $SR/(2\pi V_p)$. The requested peak uses low-frequency gain; the slew utilization uses the attenuated linear peak. Swing limits are the rails moved inward by the entered headrooms, and the swing margin includes the output DC level.

The signed output error is $NV_{OS}+R_f I_- - N R_+ I_+$. Current is positive into a pin, and positive offset raises the output. With zeroed ideal sources, $R_-=R_f/N$; balancing $R_+=R_-$ cancels equal signed currents. Difference mode has this balance inherently; non-inverting mode uses the entered source resistance. The + input pin DC voltage is its unloaded Thevenin voltage minus $I_+R_+$ in every topology; this loaded voltage is used in the common-mode margin. See SLOD006B chapters 10–11, especially printed p. 11-10 (attached p. 180), for offset, bias definitions and source loading.

The waveform uses a behavioral single pole with each sample increment bounded by $SR\,\Delta t$ and then clamped to the output swing limits. The initial state is solved from the one-cycle fixed point. Two bracketed searches, each capped at 40 iterations of 256 sample intervals, locate the ends of the periodic-state interval; its midpoint avoids arbitrary DC offsets when severe sampled slew clamping makes the fixed point non-unique. An analytical fast path handles unconstrained linear operation. A canonical phase is solved first and the periodic samples are then shifted to the requested phase, avoiding phase-dependent startup transients. The canonical cycle closure is checked independently before wrapping; a residual above 0.1 µV produces a warning. The finite iteration budget bounds runtime. This remains an illustration of limiting, not a distortion or saturation-recovery prediction.

Preferred resistor selection minimizes absolute resistance difference, checks adjacent decades and breaks ties toward the lower value. E12/E24 values follow Vishay Sfernice Standard Ohmic Values; E96 is generated from the rounded three-significant-digit geometric progression. Suggestions use E24 when Exact is selected. No standard table or figure is reproduced.

• A dominant-pole, voltage-feedback op amp with sufficiently high open-loop DC gain; $f_c\approx GBW/N$.
• Ideal, low-impedance signal sources; the non-inverting source resistance affects both output bias error and input common-mode voltage. No source capacitance or parasitic feedback poles.
• Difference resistors have exactly matched ratios and a grounded reference; resistor tolerance and CMRR error are omitted.
• Input offset and bias currents are signed, constant values. Common-mode checks include the DC bias-current drop at the + input, with the linear signal amplitude; input protection and offset-induced differences between pins are omitted.
• Symmetric, constant slew rate and hard output swing limits. Headrooms must be entered for the intended load, supply and temperature.
• Defaults are a generic example, not guaranteed limits for a named op amp. Equations and original drawings are implemented here from circuit laws and the cited methods.

Use this calculator for preliminary gain and sinusoidal signal checks in resistive stages. Small-signal bandwidth is an estimate, not guaranteed data-sheet performance. A zero summed AC amplitude leaves the full-power frequency blank because no AC slew requirement remains.

The output waveform is an illustrative sampled behavioral model. It omits overload recovery, input protection, finite open-loop DC gain, noise, distortion, output-current limits and temperature drift. The displayed cycle is periodic within the stated closure tolerance. If the bounded solver does not verify closure, a warning is shown; use the analytical gain and limit checks until it clears. Phase shifting uses linear interpolation on the 256-interval cycle, so extrema between samples have finite resolution. Extremely low or high pole-to-signal ratios can make the behavioral shape less accurate.

Capacitive-load stability is not calculated. Load capacitance, high feedback resistance, input capacitance and layout can add poles and reduce phase margin. Check the device data sheet, any minimum stable noise gain, and the required isolation/compensation network. Current-feedback amplifiers are outside this model.