Inverter Loss and Heatsink Calculator

Thermal results are cycle averages. A separate periodic peak-junction check is required before selecting a heatsink, especially at low output frequency.

Commanded modulation and dead-time validity

The input $m$ is the sinusoidal PWM command, before dead time. The ideal fundamental phase peak is $mV_{dc}/2$. The conduction calculation transfers the blanking interval from IGBT to diode; no active voltage compensation is assumed. Voltage, output power, efficiency and capacitor-current estimates retain the ideal commanded fundamental and are labeled accordingly.

Berg and Roinila, §II.A, give the switching-cycle voltage-error amplitude $V_{dc}f_{sw}t_d$. For sinusoidal current its square-wave fundamental amplitude is $\Delta V_1=4V_{dc}f_{sw}t_d/\pi$. The relative screen is therefore $\epsilon=8f_{sw}t_d/(\pi m)$. This calculator warns above 5% and refuses results above 10%. These percentages are chosen screening limits for this approximation, not accuracy guarantees or thresholds stated by the paper. It does not solve the effective voltage phasor or current response.

Device currents and losses

Graovac and Pürschel (2009), §§2 and 3.4, provide the piecewise-linear forward model and sinusoidal inverter current averaging. Let $I_p=\sqrt{2}I_{\mathrm{phase}}$, $k=m\cos\varphi$, and $\delta=f_{\mathrm{sw}}t_d$. Integrating the positive-current half-cycle with current $i=I_p\sin\theta$ and transistor duty $(1+m\sin(\theta+\varphi))/2-\delta$ gives

The complementary diode values follow from $I_{D,av}=I_p/\pi-I_{T,av}$ and $I_{D,rms}^2=I_{\mathrm{phase}}^2/2-I_{T,rms}^2$. The dead-time terms are derived here by transferring the same current interval from IGBT to diode. Duty clipping is excluded by $m+2\delta\leq1$.

For each device, $P_c=V_0 I_{av}+r I_{rms}^2$. Assuming each event energy is linear in current and switched voltage, half-cycle integration gives $P_{sw,T}=f_{\mathrm{sw}}(E_{on}+E_{off})I_pV_{dc}/(\pi I_{ref}V_{ref})$, with the analogous expression for diode $E_{rec}$. Switching loss is counted once in each dissipating device. Six transistor/diode pairs form the inverter.

Cycle-average heatsink, including base spreading

Each phase module dissipates $P_m=2(P_T+P_D)=P_{loss}/3$. Divide the shared base into three equal strips along its length; each identical module is centered in its strip. With uniform cooling and insulated outer edges, symmetry makes the internal strip boundaries adiabatic. This equal-region reduction is derived here; Lee's published example verifies the single-region correlation.

For one region, use source area $A_s$, region area $A_p=L_bW_b/3$, average region resistance $R_0=3R_{sa}$, conductivity $k$ and base thickness $t$. Lee (1998), Eqs. (1)–(2), credits Song, Lee and Au (1994). In an equivalent algebraic form, define
$\lambda=\frac{\pi^{3/2}}{\sqrt{A_p}}+\frac{1}{\sqrt{A_s}},\quad u=\tanh(\lambda t),\quad b=\lambda kA_pR_0,$
$R_{sp}=\frac{1/\sqrt{A_s}-1/\sqrt{A_p}}{k\sqrt{\pi}}\frac{b+u}{1+bu}.$
This is the maximum local excess over the mean base temperature per watt of one module. The applied correction is zero when spreading is disabled.

The spatial hot spot is on the source-side heatsink base:
$T_{hot}=T_a+P_{loss}R_{sa}+P_mR_{sp},\qquad R_{hot,total}=R_{sa}+R_{sp}/3.$
Thus the equivalent total sink resistance is referred to total inverter loss, while $R_0+R_{sp}$ refers to one region's module power. The case is above this base hot spot by $P_mR_{cs}$. Each junction adds its own $P_TR_{jc,T}$ or $P_DR_{jc,D}$; using the maximum base temperature for both junction paths is a preliminary thermal-chain estimate.

The average source-side sink resistance already includes uniform conduction through the full base. Fourier's law gives the physical floor

When spreading is enabled, require $R_{sa}\geq R_{base}$. This follows by averaging the steady conduction equation across the insulated-sided base: $-kA_{base}\,d\overline{T}/dz=P_{loss}$. Even an isothermal fin-side boundary cannot remove that through-thickness rise. Ockfen (2023), Eq. (4), uses the same slab-resistance relation. This floor is part of the entered average resistance; it is not added again.

The average sink-resistance ceiling is found by solving
$P_{loss}[r+R_{sp}(3r)/3]+P_mR_{cs}+\max(P_TR_{jc,T},P_DR_{jc,D})=T_{limit}-T_a.$
Spreading is recomputed at each candidate $r$, with $r\geq R_{base}$ when enabled. Test feasibility at $R_{base}$, including its local spreading rise, before searching for a root. A zero ceiling indicates that no physically feasible sink meets the target; it is not a recommendation to use zero thermal resistance. The lowest possible cycle-average junction temperature uses this same ideal fin-side cooling boundary. Zero loss and invalid footprint geometry are caught before the solver runs; the input conditions explain how to correct them.

The thickness and footprint charts hold the entered full-base average sink resistance, operating losses and all other dimensions fixed. Both contact dimensions scale together in the area sweep. They isolate the spreading effect; obtain new average sink data if changing the real base or airflow. Thickness points with $t>kA_{base}R_{sa}$ are omitted, because they would require negative resistance between the fin-side boundary and ambient. Thickness does not have a universal monotonic benefit.

Capacitor current

Karanayil, Agelidis and Pou, §II Eq. (1), give the ideal sinusoidal-current expression

Gohil et al., attached PDF pp. 3–5, explain switching-state current summation and a fuller ripple-inclusive method. This tool implements the sinusoidal-current approximation only. It computes an RMS from mean square; it does not average local RMS values as printed in their Eq. (24).

Fixed-case pulse

The Infineon Foster form is $Z(t)=R_{jc,T}\{a[1-e^{-t/\tau_f}]+(1-a)[1-e^{-t/\tau_s}]\}$. A rectangular pulse uses $P_T[Z(t)-Z(\max(t-t_p,0))]$. The initial junction equals the independently specified fixed case temperature. The two resistance fractions sum exactly to the steady junction-to-case resistance. Cauer networks represent physical layer nodes; Foster internal nodes do not. No Foster sink network is concatenated here.

• Balanced three wire, three phase motoring operation; six identical IGBTs and six identical anti-parallel diodes, grouped into three equal half-bridge modules.
• Continuous sine-triangle PWM in the linear range, with enough carrier cycles to average over the fundamental. Phase current is sinusoidal; leading and lagging displacement factors give the same average losses.
• A single effective dead-time interval per carrier period is transferred from transistor to diode. Current ripple, voltage-drop feedback on the commanded modulation, minimum-pulse suppression and switching during dead time are omitted.
• Datasheet forward fits and switching energies are held at a chosen hot temperature and actual gate-drive conditions. There is no automatic electrothermal iteration or device catalogue. All device, interface and Foster defaults are illustrative.
• Linear switching-energy scaling has zero intercept. Output-capacitance energy at zero current, leakage, gate-drive, snubber, busbar, magnetic and capacitor ESR losses are excluded.
• Cycle-average thermal quantities only. Three equal modules occupy the centers of three equal base regions in one row, with uniform cooling, insulated outer edges and constant conductivity. Heat flux is uniform over each effective module footprint. Both junction types use the same temperature target.
• Lee's central-source, area-based correlation is applied per region. Footprints must fit; source and region aspect ratios must not exceed 2.5. Unequal module losses, irregular spacing, edge-mounted sources, localized airflow and internal die-scale heat spreading need a spatial model.
• The entered full-base sink resistance describes its area-average source-side temperature, including uniform base conduction. Turn off the added spreading correction when the sink data already include the actual footprint and layout. No automatic fin-spreading or 20% thickness adjustment is applied.
• The optional Foster pulse applies the calculated average IGBT dissipation as a rectangular heating envelope at fixed case temperature. It does not resolve fundamental-frequency junction ripple or reproduce a particular named module.
• Each temperature has one input stored in Celsius. The viewer converts absolute temperature inputs and results with the correct offset. Temperature differences and thermal resistances use K and K/W; diagram labels show temperature rises.
• Modulation and displacement angle refer to the voltage command before dead time. No dead-time voltage compensation is assumed. Ideal voltage, power, efficiency and capacitor estimates omit that voltage error; the explicit 5% warning and 10% refusal thresholds bound their use as preliminary estimates.
• When spreading is enabled, heat leaves through the far side of the insulated-sided base. Its average resistance cannot fall below t/(k × full base area). The base geometry is not applied when spreading is disabled and the user supplies layout-specific thermal data.

Average-temperature headroom is not peak-temperature headroom. This tool does not calculate periodic junction-temperature ripple. A positive average headroom or a sink below the reported ceiling does not prove that the device peak temperature remains below its rating. Use the actual device thermal network and periodic loss waveform for that separate check, especially at low output frequency.

Use only with estimated dead-time fundamental error no larger than 10% of the commanded phase-voltage peak, $0<m\leq1$, $0\leq\cos\varphi\leq1$ and $m+2f_{sw}t_d\leq1$. The model warns below ten carrier cycles per fundamental cycle. Duty clipping, discontinuous PWM, zero-sequence injection, unbalanced loads, regenerative operation and synchronous MOSFET conduction are outside scope.

Use hot typical values for typical estimates or suitably conservative device data for a design bound. Supply switching energies near the operating current, voltage, junction temperature and gate resistance. Check voltage overshoot, current rating, safe operating area and thermal cycling separately. The efficiency is a semiconductor-only estimate.

The capacitor estimate excludes output-current switching ripple and source-side ripple; it is not a complete capacitor selection or voltage-ripple calculation. The modulation sweep holds phase RMS current and displacement factor fixed and ignores dead time.

A zero permitted heatsink resistance means that no physical sink meets the target with the specified base and module. With spreading enabled, the average sink resistance must include at least t/(k × full base area); a smaller entered value is rejected. Invalid footprint geometry and zero loss suppress sizing results without entering the root solver. Thermal interface values must describe a complete phase module; using a per-chip interface value with full module power would overestimate its rise.

Pulse coefficients must be fitted to the actual datasheet curve. Very short pulses need a suitable higher-order model; a two-term fit cannot reproduce every device. Keep the case fixed for this calculation. Foster internal nodes are not physical layer temperatures, and no Cauer transient solution or cold-start heatsink prediction is provided.

At low commanded modulation, dead-time voltage error can dominate the fundamental even when the duty-clipping condition passes. The voltage-error estimate also neglects zero-crossing clamping, current ripple and switching-device voltage drops. Do not interpret ideal commanded voltage or power as a prediction of the actual terminal waveform.

Lee's model estimates the spatial maximum on a uniformly heated module footprint; it does not resolve a module's individual die temperature map or fin spreading. The equal-region extension is limited to the stated symmetric layout. The hot-spot temperature reported here is still a cycle average, not a transient maximum. Do not add this correction to supplier data already measured for the same source footprints and placement. Geometry sweeps are sensitivity studies with average sink resistance held fixed, not a convection design or proof of an optimum base thickness.