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PDN Target Impedance and Decoupling Capacitor Planner

Size a three-value decoupling bank using target impedance, ESR, ESL and mounting inductance. Plot impedance, find anti-resonance peaks and estimate capacitor counts.

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Published 29. October 2026 · version 2 of 6. November 2026

#anti-resonance #decoupling capacitors #ESL #ESR #PDN #power integrity #target impedance

Plan a decoupling capacitor bank for a digital power rail, compare its impedance with a target, and see why mixing capacitor values can create anti-resonance peaks. This PDN target impedance calculator is intended for PCB engineers, students learning power integrity, and designers comparing early decoupling strategies.

Start with the nominal rail voltage, the permitted one-sided AC ripple and the actual load current change. Enter ripple as a percentage: 5 means 5%. Reserve enough of the device voltage tolerance for regulator accuracy, DC voltage drop and other noise before assigning the remaining budget here. The target impedance is the allowed voltage excursion divided by the load current change. The frequency band is an explicit design input; choose it from the load spectrum and the range assigned to board-level capacitors.

Configure up to three capacitor groups. Each group has a part count, effective capacitance, ESR, body ESL and mounting loop inductance. Group A remains present; setting the count of group B or C to zero omits it. Enter effective capacitance after DC bias, tolerance, temperature and aging effects. Default component values illustrate the circuit model and do not identify orderable parts. Vendor impedance data or a validated equivalent circuit should replace them for a real design.

The schematic shows the parallel bank at the load port. Each physical capacitor is represented by capacitance, resistance and inductance in series. The mounting value is the additional complete supply-and-return loop for that part. Do not enter a shared via or a common board path as if every capacitor had an independent copy.

Inspect the bank impedance against the target line across the whole band. The separate single-part curves show where each value changes from capacitive to inductive behavior. Between resonances, inductive and capacitive branch currents can cancel, creating an impedance peak. Lower ESR can make that peak sharper, so adding a different capacitor value does not always improve the bank.

The recommended counts preserve your chosen proportions. The planner calculates the smallest integer number of whole copies of the selected bank needed by the numerical model, and reports both the resulting counts and additional parts. It does not search all possible combinations or optimize PCB area, cost or placement. Compare alternatives by changing values, counts and mounting inductance.

This is a lumped capacitor-bank calculation. It omits regulator dynamics, common spreading and package inductance, mutual coupling, plane resonances and on-die capacitance. Meeting its target is a screening result rather than proof of transient compliance. Validate the full PDN with appropriate circuit or electromagnetic models and measurements at the device supply pins.

How it is calculated

The target is $Z_t=\Delta V/\Delta I$ , with $\Delta V=V_{rail}r/100$ and $r$ the entered ripple percentage. This uses a one-sided excursion budget, not peak-to-peak ripple.

The circuit equations are derived here from the series RLC impedance and Kirchhoff's current law:

L_i=L_{body,i}+L_{mount,i},\qquad Z_i(f)=R_i+j\left(2\pi f L_i-\frac{1}{2\pi f C_i}\right)

Z_{bank}(f)=\left(\sum_i\frac{n_i}{Z_i(f)}\right)^{-1},\qquad f_{s,i}=\frac{1}{2\pi\sqrt{L_iC_i}}.

Individual curves represent one mounted part; the bank includes each group's count. Opposite branch susceptances can cancel between series resonances, creating anti-resonance peaks.

The numerical search uses 401 logarithmic samples plus series resonances and roots of the lossless three-branch admittance numerator as seeds. Every detected interior local maximum is refined in log frequency with 36 ternary-search iterations. Band endpoints and refined peaks are included in the worst value and the chart.

Independent copies of the complete selected bank scale every admittance by $k$ , so $Z_k=Z_{bank}/k$ . Thus $k=\max(1,\lceil Z_{worst}/Z_t\rceil)$ and recommended counts are $k n_i$ . This is a fixed-mix numerical sizing rule, not a global optimizer.

Open method references: XAPP623 v2.1 (2005), pp.4 and 8–9, for series parasitics and mounted inductance; Altera PDN Tool User Guide (2009), Eq.1–2, for the target calculation. NXP AN2321 Rev.1 (2005), Table 1, supplies an independent rounded resonance value. The IEEE TCPMT 2022 paper is cited as related optimization research; its algorithm is not implemented.

Assumptions

Constant, positive ESR and effective capacitance; linear small-signal behavior.
All capacitors connect to the same electrically small load port through independent mounting loops. Identical parts in a group have equal parameters.
The user supplies the frequency band and the one-sided ripple budget. No bandwidth is inferred from clock frequency alone.
Component defaults are illustrative model values, not a component catalog or universal package parasitics.
The circuit equations are derived here; published worked examples independently verify target impedance and resonance.

Where it applies

Use for first-pass board-level capacitor-bank comparisons from 1 kHz to 300 MHz, within the lumped model's validity for your layout. This input range is not a guarantee that a real board remains lumped throughout it. Regulator, shared power/return paths, IC package, plane and on-die effects are excluded. Adding capacitors cannot divide shared inductance.

Peak positions and fixed-mix counts are numerical estimates. Extremely narrow or nearly coincident resonances need a denser independent sweep. Zero reported interior peak frequency/impedance means no local maximum was detected in the chosen band; a band-edge maximum is reported separately. Hidden groups retain their defaults for single-part reference curves but contribute no bank admittance.

A flat target is a design heuristic; a frequency-domain pass does not guarantee an arbitrary time-domain voltage waveform. Check bias-dependent capacitance, ESR over frequency, voltage rating, ripple current, placement and the complete PDN before committing hardware.

References

Xilinx, Mark Alexander, XAPP623 v2.1, Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors, 28 February 2005. https://docs.amd.com/api/khub/documents/rqk~alpjrAD0EGuVgnooOw/content
Altera, Power Delivery Network (PDN) Tool User Guide v2.0, March 2009, Eq.1–2 (printed p.1–7). https://docs.altera.com/api/khub/documents/jXnBcULFqrxo5HeSClLUdg/content
NXP/Freescale, T.C. Lun, AN2321 Rev.1, Designing for Board Level Electromagnetic Compatibility, October 2005, pp.6–7. https://www.nxp.com/docs/en/application-note/AN2321.pdf
Han, Bhatti and Swaminathan, A Knowledge Based Method for Optimization of Decoupling Capacitors in Power Delivery Networks, IEEE TCPMT 12(5), 828–838 (2022). DOI: 10.1109/TCPMT.2022.3170306. https://doi.org/10.1109/TCPMT.2022.3170306

Inputs

Input	Symbol	Unit	Default
Nominal rail voltage	`V_rail`	V	1
Allowed ripple (%) One-sided AC voltage allowance available to the load step. Enter 5 for 5%; subtract DC error and other noise from the budget first.	`ripple_pct`		5
Load current change ΔI Actual transient change, not total rail current.	`I_step`	A	2
Band lower limit Lowest frequency assigned to this capacitor bank. Regulator and bulk behavior below this frequency are excluded.	`f_low`	MHz	0.1
Band upper limit Select from load spectrum and package/board model validity. No edge-rate bandwidth assumption is imposed.	`f_high`	MHz	100
Parts in selected bank At least one group A part is required. Counts define one selected bank.	`n_1`		2
Effective capacitance per part Use capacitance at operating DC bias, temperature, tolerance and age. Defaults are illustrative RLC values, not vendor part specifications.	`C_1`	uF	10
ESR per part Constant positive ESR approximation. Frequency-dependent vendor data is preferable for final verification.	`R_1`	mohm	20
Body ESL per part	`Lb_1`	nH	0.5
Mounting loop inductance per part Additional complete power-and-return loop per capacitor: pads, traces and vias. Do not enter a single via inductance or shared path here.	`Lm_1`	nH	0.5
Parts in selected bank Set to zero to omit this group.	`n_2`		4
Effective capacitance per part Use capacitance at operating DC bias, temperature, tolerance and age. Defaults are illustrative RLC values, not vendor part specifications.	`C_2`	uF	1
ESR per part Constant positive ESR approximation. Frequency-dependent vendor data is preferable for final verification.	`R_2`	mohm	10
Body ESL per part	`Lb_2`	nH	0.5
Mounting loop inductance per part Additional complete power-and-return loop per capacitor: pads, traces and vias. Do not enter a single via inductance or shared path here.	`Lm_2`	nH	0.5
Parts in selected bank Set to zero to omit this group.	`n_3`		8
Effective capacitance per part Use capacitance at operating DC bias, temperature, tolerance and age. Defaults are illustrative RLC values, not vendor part specifications.	`C_3`	uF	0.1
ESR per part Constant positive ESR approximation. Frequency-dependent vendor data is preferable for final verification.	`R_3`	mohm	20
Body ESL per part	`Lb_3`	nH	0.4
Mounting loop inductance per part Additional complete power-and-return loop per capacitor: pads, traces and vias. Do not enter a single via inductance or shared path here.	`Lm_3`	nH	0.6

Results

With the default inputs above, the calc gives:

Result	Value
Target impedance	25 mohm
Worst selected-bank impedance	64.448 mohm
Worst-impedance frequency	0.1 MHz
Whole selected-bank copies needed	3
Recommended total capacitors	42
Additional capacitors	28
Worst recommended-bank impedance	21.483 mohm
Strongest interior peak (0 = none)	10.743 MHz
Strongest interior peak (0 = none)	21.684 mohm
Selected effective capacitance	24.8 uF

Checked against sources

Each case below was calculated by this calc and agrees with the value from its source (within the tolerance where one is shown).

XAPP623 mounted 10 nF capacitor: about 38 MHz

Source: Xilinx XAPP623 v2.1 (2005), pp.8–9: 0.01 µF, body ESL 0.9 nH and mounting 0.8 nH. Published 38 MHz is approximate; the stated components give 38.60 MHz, retained without adjusting the model.

Inputs: Effective capacitance per part = 0.01 uF; Body ESL per part = 0.9 nH; Mounting loop inductance per part = 0.8 nH; Parts in selected bank = 1; Parts in selected bank = 0; Parts in selected bank = 0; the others as above.

Result	Source	This calc
Group A mounted self-resonance	38 ± 0.7 MHz	38.601 MHz

XAPP623 unmounted 10 nF capacitor: about 53 MHz

Source: Xilinx XAPP623 v2.1 (2005), p.8, AVX example: 0.01 µF and 0.9 nH. Rounded source value 53 MHz; equations give 53.052 MHz.

Inputs: Effective capacitance per part = 0.01 uF; Body ESL per part = 0.9 nH; Mounting loop inductance per part = 0 nH; Parts in selected bank = 1; Parts in selected bank = 0; Parts in selected bank = 0; the others as above.

Result	Source	This calc
Group A mounted self-resonance	53 ± 0.1 MHz	53.052 MHz

NXP AN2321 surface-mount 100 nF: about 16 MHz

Source: NXP/Freescale AN2321 Rev.1 (October 2005), pp.6–7, Table 1. Surface-mount 0.1 µF with 1 nH total interconnect inductance is listed at 16 MHz (rounded); model gives 15.915 MHz. https://www.nxp.com/docs/en/application-note/AN2321.pdf

Inputs: Effective capacitance per part = 0.1 uF; Parts in selected bank = 1; Parts in selected bank = 0; Parts in selected bank = 0; the others as above.

Result	Source	This calc
Group A mounted self-resonance	16 ± 0.1 MHz	15.915 MHz

Altera worked example: 0.9 V, 5%, 2 A step → 22.5 mΩ

Source: Altera Power Delivery Network (PDN) Tool User Guide v2.0, March 2009, printed p.1–7, Eq.1–2. Published example: 0.9 V, 5% ripple and 4 A maximum current with 50% transient current gives 0.0225 Ω. https://docs.altera.com/api/khub/documents/jXnBcULFqrxo5HeSClLUdg/content

Inputs: Nominal rail voltage = 0.9 V; the others as above.