PCB Trace Width Calculator — IPC-2221 & IPC-2152

Thermal sizing

Legacy IPC-2221 fit: the historical relationship used with IPC-2221 (1998), also described against IPC-2221B (2012), is

Use amperes, degrees Celsius of rise (numerically kelvins), and square mils. The fitted coefficients are $k=0.048$ externally and $0.024$ internally. Solve for area, then divide by copper thickness. See CircuitCalculator, equations and FAQ 1a (https://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/).

IPC-2152 (2009) baseline: this is the SMPS.us regression of Jack Olson's baseline coefficients, not an official IPC formula:

The same baseline area is used for both layers. No application modifiers are implemented. See SMPS.us, equation and worked example (https://www.smps.us/pcb-calculator.html).

Geometry and electrical loss

The nominal conversion is $t=1.378q$ mil for $q$ in oz/ft², following CircuitCalculator. Thus 1 oz/ft² is 35.0012 µm. This deliberately differs from SMPS.us's approximate minimum-foil conversion; it does not alter its area fit.

Width is $w=A_c/t$. The steps normalize empirical inputs to amperes, kelvins and square mils before applying the coefficients. All length and area conversions are explicit.

Uniform-conductor physics gives $R=\rho(T)L/A_c$, $V=IR$, and $P=I^2R$. Copper is approximated by $\rho_{20}=1.72\times10^{-8}$ Ω·m and $\alpha=0.00393$ K⁻¹, as documented by TWC (https://github.com/ymic9963/twc). Here $T=T_{board}+\Delta T$. These electrical equations are derived from Ohm's law; they do not solve a coupled thermal problem.

The plotted curves are calculated from these equations; no IPC chart or table is reproduced. Each sweep sample is checked against its model's numeric domain. Out-of-range samples are omitted as gaps, and the plot coverage card counts them. The comparison table retains out-of-range point estimates with an explicit EXTRAPOLATED label. Numeric range checks do not establish construction applicability.

• A long, uniform copper conductor carries continuous DC, or low-frequency RMS current when thermal averaging is justified.
• Rectangular nominal copper cross-section. No etching taper, plating allowance, minimum thickness tolerance or automatic design margin.
• The baseline is unmodified. Copper weight changes thickness and width geometrically; its thermal correction is not included. Layer selection changes only the legacy coefficient.
• Local unpowered board temperature accounts for background heating. Electrical loss assumes uniform copper at that temperature plus the selected rise.
• Copper resistivity is linearized about 20 °C. Short traces and connection heat sinking need separate assessment.
• The diagram is an original schematic. Width and thickness are exaggerated independently; it is not a scaled stack-up.
• For the IPC-2152 baseline, both board dimensions exceed 76.2 mm (3 in). Boards that do not meet this footprint restriction need separate thermal assessment; this tool does not model their reduced heat-spreading area.

IPC-2152 baseline fit

Numeric domain: 2–100 K rise, current up to 30 A, and required cross-section 5–700 mil² (0.003226–0.451612 mm²). The area range comes from IPC's published contents (https://www.ipc.org/TOC/IPC-2152.pdf), PDF page 3, Figure 5-2 entry. A 30 A ceiling alone does not prevent area extrapolation. Values outside the area range remain visible with an EXTRAPOLATED status and a warning; they are not in-range sizing recommendations.

Both board dimensions must exceed 3 in (76.2 mm). Smaller boards require separate thermal assessment. See Jack Olson, Determining Circuit Board Current Carrying Capability (https://frontdoor.biz/PCBportal/HowTo2152.pdf), PDF page 4. Board footprint is an applicability assumption, not an input or a correction in this calculator.

The baseline construction is 0.070 in (1.778 mm) polyimide, 3 oz copper, still air, with isolated conductors separated by more than 1 in. Board thickness, material, plane coupling and copper-thickness thermal modifiers are omitted. Other copper weights are approximate geometric translations. A thin board without planes may need more copper. Selecting an internal layer does not establish an internal-stack-up model.

Legacy fit

Historical chart range: up to 35 A, 10–100 K rise, 0.5–3 oz/ft² copper, width up to 0.4 in (10.16 mm). The selected legacy result is blocked outside these limits. A comparison outside either model's range is flagged as extrapolated. Each curve is checked across the entire sweep. Out-of-range baseline areas and legacy widths are omitted as gaps; below 10 K rise the legacy curve is omitted entirely. The plot coverage card reports omitted sample counts. The remaining lines satisfy the numeric limits, subject to construction restrictions.

Design limits and verification

Not a via, pad, clearance, impedance, fusing, pulse-survival or high-frequency current-rating calculation. Neither model establishes laminate or solder-mask temperature compliance. Select allowable temperature from the actual materials and components, include manufacturing tolerances, and validate the assembled board. Check against the standard in force; this tool implements the named historical fit methods, not a certification process.

Reference cases include Cadence's 6 A and 4 A external examples, the SMPS.us chart reading and reported fit result, onsemi's nominal copper thickness, and TI's rounded internal example. TI does not state the example rise; the 10 K setting is an explicit inference. The SMPS.us 500 mil² chart reading uses a 3% local tolerance; that is not a global accuracy claim.