PCB Impedance: Microstrip, Stripline, Coplanar & Differential Pairs

Single microstrip follows Hammerstad and Jensen (1980): normalized width u = w/h, homogeneous-air impedance, dielectric filling, and separate air/dielectric finite-thickness width increments. Effective permittivity includes the ratio of the corrected homogeneous impedances. The optional Kirschning–Jansen model updates both permittivity and impedance; fₙ = f[GHz]h[mm]. See Qucs, Single microstrip line, sections Hammerstad and Jensen, Strip thickness correction, and Kirschning and Jansen. The audit's Wheeler 1977 expression uses the same HJ effective width, so the comparison isolates the impedance approximation rather than introducing a second copper correction.

Coplanar waveguide: Qucs Coplanar waveguides, equations 12.8–12.18, following Wen's conformal-mapping approach. The elliptic-integral ratio K(k)/K′(k) is evaluated with the arithmetic–geometric mean. Finite substrate thickness uses sinh without backing metal and tanh with backing metal. The first-order copper correction adjusts the surface modulus and effective permittivity as in the maintained Qucs implementation. Both coplanar grounds are continuous and effectively infinite.

Centered stripline: b = 2h + t. Cohn's zero-thickness solution uses k = tanh(πw/(2b)) and Z = Zfree/[4√εᵣ · K(k)/K′(k)]. Finite copper uses the usual wide/narrow strip approximation documented in the open KiCad stripline implementation. Cohn's coupled-strip conformal moduli give the even/odd stripline pair; finite-copper fringe-capacitance correction is used only for s ≥ 5t.

Differential microstrip: Kirschning–Jansen quasi-static modal equations, with Jansen's separate even/odd effective widths substituted in the corresponding modal model. This is a first-order finite-copper extension, not a field solution. The tool conservatively requires t/h ≤ 0.075 and s ≥ 20t. At t = 0 it is the thin-strip modal model. Zdiff = 2Zodd and Zcommon = Zeven/2; a pair is never estimated by simply doubling an isolated-line impedance.

Phase delay per length is β/ω = √εeff(f)/c; a pair uses odd-mode εeff. This follows a constant-frequency phase front. A narrowband pulse envelope instead follows group delay dβ/dω, which includes the frequency derivative of √εeff. The two differ under dispersion. Group delay and broadband digital edge timing are not calculated; use a frequency-dependent interconnect model for timing. Width or gap synthesis uses a bracketed root of the selected model. A target outside the valid bracket produces a condition message. The user-selected mask decrease multiplies external-line impedances only; uncoated phase delay is retained. The drawing shows schematic field paths, not the atlc solution.

The KJ impedance fit is screened near εᵣ = 1 because its power-law ratio can become ill-conditioned, and is limited here to f[GHz]h[mm] ≤ 20. These limits also govern the audit when dispersion is disabled for the main calculation. Outside the supported range the audit does not evaluate KJ: the row is labeled “KJ unavailable; static shown” and repeats the quasi-static value. If dispersion is enabled, the existing range conditions require correcting the inputs or disabling dispersion.

Independent numerical reference cases: atlc 4.6.1 finite-difference runs made on 27 October 2026 are attached with commands, bitmap hashes and mesh-refinement output. All use εᵣ = 4, t = 0.05 mm, h = 1 mm and no mask. Single microstrip w = 2 mm gives 49.712 Ω; centered stripline w = 1 mm gives 48.074 Ω. A microstrip pair with w = s = 1 mm gives Zodd = 61.286 Ω and Zeven = 82.159 Ω; the centered stripline pair gives 44.166 Ω and 51.669 Ω. Stripline plane spacing is 2.05 mm. External cases use 80 pixels per h, embedded cases 160, with 20h-wide boundaries. The external pair's odd-mode grid change from 40 to 80 pixels is 1.016 Ω; embedded 80-to-160 changes are under 0.24 Ω. Case tolerances include finite-grid and model error; printed solver digits do not establish accuracy. The two published Wcalc CPW air examples provide separate open-source reference values.

Uniform, straight, rectangular copper in a homogeneous, isotropic, nonmagnetic substrate; continuous reference planes and air above external traces. Centered stripline has equal dielectric clearance on both sides and the same εᵣ throughout. Coplanar grounds are symmetric and wide, with the same slot on each side; grounded CPW assumes the grounds are electrically bonded.

The entered design Dk is treated as constant at the chosen frequency; the optional microstrip dispersion model describes geometric dispersion, not the material's dielectric spectrum. Pair and CPW models are quasi-static and do not apply a single-line dispersion correction to coupled modes. Digital edge spectrum, rather than data rate alone, determines the relevant frequency.

Finished copper thickness includes plating. No roughness, etch profile, glass weave, dielectric loss, radiation loss, discontinuities, or conductor skin-effect impedance is calculated. The solder-mask percentage is supplied by the user as an allowance, with zero as the bare default; it is not inferred from a mask material. Phase delay and permittivity are always labeled uncoated. Phase delay is not a pulse-arrival or group-delay prediction when dispersion is present.

Public fab rows are dated nominal outer-layer geometry with backing copper, not impedance guarantees or stripline constructions. They cannot describe unbacked CPW. For an unbacked line, custom h is the actual substrate thickness and there must be no conductor backing the substrate. The two-layer preset's Dk is specified at 10 MHz and may be unsuitable at GHz frequencies.

The tool enforces εᵣ = 1…18, t/h ≤ 0.3, and w ≥ 5t. Width/height limits are 0.1…10 for single microstrip, 0.1…9 for differential microstrip (headroom for its thickness increment), and 0.1…5 for stripline and CPW. Gap/height is 0.1…10 for pairs and 0.1…5 for CPW.

For nonzero copper thickness, microstrip pairs additionally require t/h ≤ 0.075 and s ≥ 20t; centered stripline pairs require s ≥ 5t; CPW requires s ≥ 10t. These conservative restrictions are deliberate. For tighter external pairs, use a 2-D field solver with the actual copper and mask geometry; do not silently disregard copper thickness. Entering t = 0 explicitly selects an ideal thin conductor.

The largest modeled transverse width, dielectric height or relevant edge gap must be ≤ one tenth of the wavelength in the bulk dielectric. Centered stripline is screened using its full plane spacing b = 2h + t. This is a conservative quasi-TEM screen, not a full higher-mode analysis. Single-microstrip dispersion is additionally limited to f[GHz]h[mm] ≤ 20. Inverse intervals and the width sweep use these limits. Frequency zero denotes the static limit.

The formulas do not establish a universal production tolerance. Check the documented independent reference cases and their numerical tolerances. Mask allowance, Dk tolerance, plating and etched geometry can each outweigh differences between closed-form models. For final controlled impedance, confirm a fabricator's solver and coupon measurement.

For 1 < εᵣ < 1.1, disable the microstrip dispersion option: the impedance fit's denominator can cross zero near the air limit. The static model remains available. Pure air (εᵣ = 1) uses its exact nondispersive limit.

Fab presets include a backing conductor and are blocked for unbacked CPW, as well as centered stripline. Choose a custom stackup for unbacked CPW, enter its actual substrate thickness, and confirm there is no backing conductor. The KJ audit row uses the same frequency and near-air validity limits as the model even when the main calculation is static; an unavailable KJ row explicitly displays the static value instead. Reported delay is phase delay, not group delay or digital pulse-arrival time.