LDO vs Buck Converter: Efficiency, Heat, Ripple and Noise

LDO. Following TI SLVA079 §§1, 2, 4 and 12, input power is $V_{in}(I+I_q)$ and heat is $(V_{in}-V_o)I+V_{in}I_q$. A PMOS pass resistance is estimated from rated-load dropout divided by rated current. Junction temperature is ambient plus $\theta_{JA}P$.

Buck. The triangular-current power stage follows the volt-second and capacitor-charge relationships in TI SLVA477. The ripple and loss waveform uses ideal duty $D_0=V_o/V_{in}$; $\Delta I=V_o(1-D)/(Lf_s)$. PWM has $I_{rms}^2=I^2+\Delta I^2/12$. In the ideal constant-on-time PFM model, pulses retain the boundary-current peak $\Delta I$, pulse rate becomes $2If_s/\Delta I$, and $I_{rms}^2=2I\Delta I/3$. Integrating the ramp areas enforces charge balance. TI SNVA857 §2.3 describes the frequency reduction.

MOSFET conduction is RMS-current squared times duty-weighted on-resistance; inductor copper loss uses full-cycle RMS current. Switching overlap uses each edge's current and its rise/fall time. Gate-driver charging loss is $Q_gV_gf$. For an internal linear gate supply, its additional heat is $(V_{in}-V_g)Q_gf$, so total gate-related input power is $V_{in}Q_gf$ (TI SSZTBF1, equations 1–4). Both parts heat the buck IC. An external rail supplied from the same battery instead requires $Q_gV_gf/\eta_g$; its conversion loss heats the external supply. Bias loss is $V_{in}I_q$, capacitance loss is $C_{oss}V_{in}^2f/2$, and diode dead-time and recovery losses are added. Core/AC winding loss scales with pulse rate. Output ESR loss uses capacitor RMS current. These loss categories follow ROHM Rev.004 §§1–9. Only IC losses heat the buck IC; magnetic, output capacitor and external gate-supply conversion losses remain external.

Ripple and noise. The piecewise-linear current has analytical Fourier coefficients, evaluated through real sine and cosine terms to avoid complex-arithmetic overhead. Each harmonic sees $ESR+1/(j2\pi f C)$. RMS powers are summed inside the selected band. Log-frequency PCHIP interpolation supplies PSRR; harmonic voltage is multiplied by $10^{-PSRR/20}$, as defined in ADI AN-1120. The LDO's intrinsic noise is added in quadrature. Cascade broadband buck noise is conservatively attenuated by the smallest PSRR in the band. The unfiltered p-p estimate adds the exact capacitive charge swing to ESR swing; these extrema need not coincide. The ripple trough is obtained from the capacitor-charge polynomials plus ESR, after subtracting their cycle mean. If the harmonic count ends inside the noise band, Parseval's identity and the exact time-domain mean-square voltage bound the remaining energy. All unresolved energy is conservatively assigned to the band, with the largest LDO transmission in that band.

Cascade and selection. The buck supplies $V_o+H$ and load $I+I_{q,LDO}$. Total losses include both stages. Cascade dropout is checked at the estimated buck ripple trough. Following the nonideal volt-second method in TI SSZTCO3, PWM regulation requires $D=(V_o+I(R_d+R_l))/(V_{in}-I(R_h-R_l))$. Both MOSFET resistances and inductor DCR therefore enter the duty check. Eligibility and battery cutoff use the division-free margin $D_{max}[V_{in}-I(R_h-R_l)]-V_o-I(R_d+R_l)$, which is negative if the duty denominator is nonpositive. The cascade uses its intermediate voltage and load including LDO ground current. Internal gate-rail availability is checked at each input voltage. Selection minimizes input power after applying current, duty, thermal, dropout and in-band RMS AC limits. The first power-only LDO/buck crossover between 1 µA and 10 A is found by bracketed root searches on each continuous mode branch; a bias-current jump at the PFM/PWM boundary is not accepted as equal power. A blank crossover result means no root was found in that interval; the direction of the power advantage can differ between crossings.

Battery. Midpoint integration of $dt=dQ\,V_{bat}/P_{in}$ follows a linear voltage-versus-charge curve and stops at the first electrical or thermal failure. Instantaneous constant-voltage runtime is also retained in the calculation steps.

Steady load; synchronous buck; small output ripple; ideal ramps and regulated target voltage. On-resistances, DCR, dropout and ground currents are entered at the intended operating temperature; no automatic temperature coefficient is invented. MOSFETs, gate driver and the optional internal linear gate supply share one thermal package. The default gate rail is 3.3 V. An internal rail requires input voltage at least equal to the drive voltage; zero gate-regulator dropout is assumed. For an external gate rail, its entered efficiency refers to conversion from the same battery, while its heat remains outside the buck IC.

Defaults are illustrative engineering inputs. The buck resistances, inductance, frequency, edge times, hard-switched capacitance and gate charge align with the open ROHM example, with bias and noise settings chosen for comparison. PSRR values are an editable illustrative curve, not a specified device. Apply a curve valid for the worst load and minimum headroom of both LDO paths. Noise sources are uncorrelated; intrinsic RMS inputs refer to the selected band.

PFM consists of one boundary-current pulse followed by idle time. PWM/PFM bias currents are separate. Include control and gate-supply no-load currents referred to the main input, but exclude the dynamic gate-charge current already modeled. External gate-supply efficiency excludes no-load losses included in those bias inputs. Core and AC winding loss must be supplied for this ripple swing. Battery capacity is usable charge at the stated conditions; voltage falls linearly with charge removed.

Fourier coefficients and capacitor-charge integrals are derived here from the ideal current ramps; the cited application notes provide the regulator definitions, loss categories and mode-transition context.

Loss estimation is a first-order triangular-waveform model, not a controller or transistor simulation. Resistive drops do not modify the ideal ripple slopes; the duty/headroom check uses average-current PWM volt-second balance with both MOSFET resistances and DCR. This is also the full-rate headroom criterion in PFM; actual PFM pulse-width limits need checking. A nonpositive duty denominator is infeasible and the required-duty result is blank. Use gate charge, switching times and hot on-resistances valid for the entered gate voltage. Check real gate-regulator dropout and driver UVLO; an unavailable internal rail excludes both buck options and ends their battery discharge. External gate-supply efficiency is treated as constant over the sweep. Separate θJA values assume negligible thermal coupling between packages. Verify actual duty, minimum on/off times, IC absolute ratings, LDO stability, load transients and inductor saturation. Reverse recovery is neglected in PFM because pulses start at zero current; the entered charge is applied in PWM. Input capacitor ESR, low-side switching overlap, PCB losses, parasitic ringing and EMI are not included. Source-ripple transfer through the buck's own control loop is not modeled; source sine ripple applies to the direct LDO path.

The PSRR curve is held at its endpoint outside 10 Hz–100 MHz. Real rejection changes with load, headroom, capacitor and layout. Harmonic filtering uses magnitude, so no time-domain cascade p-p value is asserted. Increase the harmonic count to sharpen very-light-load results. When the spectrum ends below the band edge, the RMS result is an upper estimate: omitted harmonic energy is bounded from the exact capacitor/ESR waveform integral. This also assigns out-of-band tail energy to the band and can overestimate the cascade's filtered periodic component substantially. The bound prevents optimistic noise eligibility on the map; a tight noise budget may therefore require more harmonics or a measured spectrum. Harmonic bars show the first 16 orders, including orders outside the RMS budget's band.

At defaults the map solves 41 × 31 points with 160 harmonics using the same harmonic model, then interpolates input powers and signed eligibility margins along both axes with PCHIP before classifying a 256 × 256 display with discrete topology colours. The solved grid and harmonic count keep the full calculation under about three seconds; narrow regions and boundaries can move by a solved interval (about 0.22 V and 0.17 load decades at defaults). Increase map samples or use the exact operating-point comparison near a boundary. Do not interpret an interpolated boundary as a component rating.

Projected losses and efficiencies are displayed for comparison even when an option is outside limits; only eligible options can win. Battery runtime ends at electrical or thermal cutoff and does not imply the noise limit is met throughout discharge. The midpoint cutoff has one discharge-interval uncertainty; refine the interval count for a marginal case. No battery impedance, rate effect, self-discharge, ageing, UVLO, charger, protection or temperature-dependent capacity model is included.